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[GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional code

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On behalf of Shiva Chen

2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
	(atomic_store<mode>): Likewise.

2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* gcc.target/arm/stl-cond.c: New test.

From-SVN: r224269
This commit is contained in:
Shiva Chen 2015-06-09 08:15:23 +00:00 committed by Kyrylo Tkachov
parent d9c16ed274
commit 99e9cec839
4 changed files with 36 additions and 6 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2015-06-09 Shiva Chen <shiva0217@gmail.com>
* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
(atomic_store<mode>): Likewise.
2015-06-09 Richard Biener <rguenther@suse.de>
* cfgloop.c (get_loop_body_in_bfs_order): Fix assert.

14
gcc/config/arm/sync.md
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@ -75,11 +75,12 @@
{
enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
return \"ldr<sync_sfx>\\t%0, %1\";
return \"ldr%(<sync_sfx>%)\\t%0, %1\";
else
return \"lda<sync_sfx>\\t%0, %1\";
return \"lda<sync_sfx>%?\\t%0, %1\";
}
)
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
(define_insn "atomic_store<mode>"
[(set (match_operand:QHSI 0 "memory_operand" "=Q")
@ -91,11 +92,12 @@
{
enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
return \"str<sync_sfx>\t%1, %0\";
return \"str%(<sync_sfx>%)\t%1, %0\";
else
return \"stl<sync_sfx>\t%1, %0\";
return \"stl<sync_sfx>%?\t%1, %0\";
}
)
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic,
;; even for a 64-bit aligned address. Instead we use a ldrexd unparied

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2015-06-09 Shiva Chen <shiva0217@gmail.com>
* gcc.target/arm/stl-cond.c: New test.
2015-06-09 Richard Biener <rguenther@suse.de>
PR middle-end/66413

19
gcc/testsuite/gcc.target/arm/stl-cond.c Normal file
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@ -0,0 +1,19 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arm_ok } */
/* { dg-require-effective-target arm_arch_v8a_ok } */
/* { dg-options "-O2 -marm" } */
/* { dg-add-options arm_arch_v8a } */
struct backtrace_state
{
int threaded;
int lock_alloc;
};
void foo (struct backtrace_state *state)
{
if (state->threaded)
__sync_lock_release (&state->lock_alloc);
}
/* { dg-final { scan-assembler "stlne" } } */