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re PR target/20813 (ICE in gen_reg_rtx for 3 spec tests)

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PR target/20813
	* config/rs6000/default64.h (TARGET_DEFAULT): Add MASK_PPC_GFXOPT.
	* config/rs6000/rs6000.c (processor_target_table): Rename rs64a to
	rs64.  Add MASK_PPC_GFXOPT to powerpc64 and rs64.
	(rs6000_init_libfuncs): Set TFmode optabs to xlq names if
	TARGET_XL_COMPAT.
	* doc/invoke.texi (PowerPC options): Change rs64a to rs64.

From-SVN: r98562
This commit is contained in:
David Edelsohn 2005-04-22 14:36:30 +00:00 committed by David Edelsohn
parent e6ef8d816e
commit 98c41d988c
4 changed files with 31 additions and 9 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2005-04-22 David Edelsohn <edelsohn@gnu.org>
PR target/20813
* config/rs6000/default64.h (TARGET_DEFAULT): Add MASK_PPC_GFXOPT.
* config/rs6000/rs6000.c (processor_target_table): Rename rs64a to
rs64. Add MASK_PPC_GFXOPT to powerpc64 and rs64.
(rs6000_init_libfuncs): Set TFmode optabs to xlq names if
TARGET_XL_COMPAT.
* doc/invoke.texi (PowerPC options): Change rs64a to rs64.
2005-04-22 Nathan Sidwell <nathan@codesourcery.com>
* lambda-code.c: Define VEC(int,heap), VEC(lambda_loop,heap).

3
gcc/config/rs6000/default64.h
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@ -21,4 +21,5 @@ Boston, MA 02111-1307, USA. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_POWERPC | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS)
(MASK_POWERPC | MASK_PPC_GFXOPT | \
MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS)

25
gcc/config/rs6000/rs6000.c
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@ -1161,14 +1161,15 @@ rs6000_override_options (const char *default_cpu)
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
POWERPC_BASE_MASK | MASK_POWERPC64},
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
{"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
{"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
{"rs64", PROCESSOR_RS64A,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
};
const size_t ptt_size = ARRAY_SIZE (processor_target_table);
@ -8139,11 +8140,21 @@ rs6000_init_libfuncs (void)
set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
}
/* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
/* AIX/Darwin/64-bit Linux quad floating point routines. */
if (!TARGET_XL_COMPAT)
{
set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
}
else
{
set_optab_libfunc (add_optab, TFmode, "_xlqadd");
set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
}
}
else
{

2
gcc/doc/invoke.texi
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@ -10565,7 +10565,7 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.