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[multiple changes]
2003-04-05 Andrew Pinski <apinski@apple.com> * config/rs6000/rs6000.c (addrs_ok_for_quad_peep): Allow addr2 reg with reg1 == reg2 and offset1 = -8. 2003-04-05 David Edelsohn <edelsohn@gnu.org> * config/rs6000/rs6000.c (rs6000_rtx_costs): Halve Power4 multiply costs. Correct Power4 divide costs. * config/rs6000/power4.md: Restore multiply and FP latency. From-SVN: r65274
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@ -1,3 +1,14 @@
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2003-04-05 Andrew Pinski <apinski@apple.com>
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* config/rs6000/rs6000.c (addrs_ok_for_quad_peep): Allow addr2
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reg with reg1 == reg2 and offset1 = -8.
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2003-04-05 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.c (rs6000_rtx_costs): Halve Power4
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multiply costs. Correct Power4 divide costs.
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* config/rs6000/power4.md: Restore multiply and FP latency.
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2003-04-05 Zdenek Dvorak <rakdver@atrey.karlin.mff.cuni.cz>
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* alias.c (find_base_term): Export.
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@ -104,7 +104,7 @@
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"(du1_power4+du2_power4+du3_power4+du4_power4),\
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iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
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(define_insn_reservation "power4-load-update-indexed" 4 ; 3
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(define_insn_reservation "power4-load-update-indexed" 3
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(and (eq_attr "type" "load_ux")
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(eq_attr "cpu" "power4"))
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"du1_power4+du2_power4+du3_power4+du4_power4,\
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@ -197,7 +197,7 @@
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(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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(define_insn_reservation "power4-lmul-cmp" 8 ; 7
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(define_insn_reservation "power4-lmul-cmp" 7
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(and (eq_attr "type" "lmul_compare")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
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@ -207,7 +207,7 @@
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(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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(define_insn_reservation "power4-imul-cmp" 6 ; 5
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(define_insn_reservation "power4-imul-cmp" 5
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(and (eq_attr "type" "imul_compare")
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(eq_attr "cpu" "power4"))
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"(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
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@ -217,7 +217,7 @@
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(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
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(define_insn_reservation "power4-lmul" 8 ; 7
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(define_insn_reservation "power4-lmul" 7
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(and (eq_attr "type" "lmul")
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(eq_attr "cpu" "power4"))
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"(du1_power4,iu1_power4*6)\
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@ -227,7 +227,7 @@
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; |(du3_power4,nothing,iu2_power4*6)\
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; |(du4_power4,nothing,iu2_power4*6)")
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(define_insn_reservation "power4-imul" 6 ; 5
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(define_insn_reservation "power4-imul" 5
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "power4"))
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"(du1_power4,iu1_power4*4)\
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@ -237,7 +237,7 @@
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; |(du3_power4,nothing,iu2_power4*4)\
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; |(du4_power4,nothing,iu1_power4*4)")
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(define_insn_reservation "power4-imul3" 5 ; 4
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(define_insn_reservation "power4-imul3" 4
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(and (eq_attr "type" "imul2,imul3")
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(eq_attr "cpu" "power4"))
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"(du1_power4,iu1_power4*3)\
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@ -305,7 +305,7 @@
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"du1_power4,iu1_power4")
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; Basic FP latency is 6 cycles
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(define_insn_reservation "power4-fp" 7 ; 6
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(define_insn_reservation "power4-fp" 6
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(and (eq_attr "type" "fp,dmul")
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(eq_attr "cpu" "power4"))
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"fpq_power4")
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@ -7331,7 +7331,11 @@ addrs_ok_for_quad_peep (addr1, addr2)
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offset1 = 0;
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}
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/* Make sure the second address is a (mem (plus (reg) (const_int))). */
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/* Make sure the second address is a (mem (plus (reg) (const_int)))
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or if it is (mem (reg)) then make sure that offset1 is -8 and the same
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register as addr1. */
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if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
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return 1;
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if (GET_CODE (addr2) != PLUS)
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return 0;
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@ -13744,8 +13748,8 @@ rs6000_rtx_costs (x, code, outer_code, total)
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case PROCESSOR_POWER4:
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*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
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? GET_MODE (XEXP (x, 1)) != DImode
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? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
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: COSTS_N_INSNS (4));
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? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
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: COSTS_N_INSNS (2));
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return true;
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default:
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@ -13807,7 +13811,6 @@ rs6000_rtx_costs (x, code, outer_code, total)
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case PROCESSOR_PPC620:
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case PROCESSOR_PPC630:
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case PROCESSOR_POWER4:
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*total = (GET_MODE (XEXP (x, 1)) != DImode
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? COSTS_N_INSNS (21)
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: COSTS_N_INSNS (37));
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@ -13823,6 +13826,12 @@ rs6000_rtx_costs (x, code, outer_code, total)
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*total = COSTS_N_INSNS (23);
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return true;
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case PROCESSOR_POWER4:
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*total = (GET_MODE (XEXP (x, 1)) != DImode
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? COSTS_N_INSNS (18)
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: COSTS_N_INSNS (34));
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return true;
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default:
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abort ();
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}
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