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invoke.texi (RS/6000 and PowerPC Options): Add -mmfcrf, -mpopcntb, -mfprnd.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add -mmfcrf,
-mpopcntb, -mfprnd. Add -mcpu=power5+.
* configure.ac: Add test for FP rounding instructions.
* configure: Regenerate.
* config.in: Regenerate.
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
_ARCH_PPCSQ, _ARCH_PPCGR, _ARCH_PWR4, _ARCH_PWR5, _ARCH_PWR5X if
features enabled.
* config/rs6000/rs6000.opt (mfprnd): New.
* config/rs6000/rs6000.c (processor_target_table): Add power5+.
(POWERPC_MASKS): Add MASK_POPCNTB and MASK_FPRND.
* config/rs6000/aix52.h (ASM_CPU_SPEC): Add -mpower5+.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mpower5+.
(TARGET_FPRND): New.
* config/rs6000/rs6000.md (UNSPEC_FRIM, UNSPEC_FRIN, UNSPEC_FRIP,
UNSPEC_FRIZ): New.
(btrunc<mode>2): New.
(ceil<mode>2): New.
(floor<mode>2): New.
(round<mode>2): New.
From-SVN: r106938
This commit is contained in:
David Edelsohn
David Edelsohn
parent
f47bddec0c
commit
9719f3b792
@ -1,3 +1,26 @@
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2005-11-14 David Edelsohn <edelsohn@gnu.org>
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* doc/invoke.texi (RS/6000 and PowerPC Options): Add -mmfcrf,
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-mpopcntb, -mfprnd. Add -mcpu=power5+.
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* configure.ac: Add test for FP rounding instructions.
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* configure: Regenerate.
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* config.in: Regenerate.
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* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
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_ARCH_PPCSQ, _ARCH_PPCGR, _ARCH_PWR4, _ARCH_PWR5, _ARCH_PWR5X if
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features enabled.
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* config/rs6000/rs6000.opt (mfprnd): New.
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* config/rs6000/rs6000.c (processor_target_table): Add power5+.
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(POWERPC_MASKS): Add MASK_POPCNTB and MASK_FPRND.
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* config/rs6000/aix52.h (ASM_CPU_SPEC): Add -mpower5+.
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* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mpower5+.
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(TARGET_FPRND): New.
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* config/rs6000/rs6000.md (UNSPEC_FRIM, UNSPEC_FRIN, UNSPEC_FRIP,
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UNSPEC_FRIZ): New.
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(btrunc<mode>2): New.
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(ceil<mode>2): New.
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(floor<mode>2): New.
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(round<mode>2): New.
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2005-11-14 Geoffrey Keating <geoffk@apple.com>
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* gcc.c (version_compare_spec_function): Use fatal() rather than
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@ -161,6 +161,12 @@
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#endif
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/* Define if your assembler supports fprnd. */
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#ifndef USED_FOR_TARGET
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#undef HAVE_AS_FPRND
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#endif
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/* Define if your assembler supports the --gdwarf2 option. */
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#ifndef USED_FOR_TARGET
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#undef HAVE_AS_GDWARF2_DEBUG_FLAG
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@ -61,6 +61,7 @@ do { \
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%{mcpu=power3: -m620} \
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%{mcpu=power4: -m620} \
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%{mcpu=power5: -m620} \
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%{mcpu=power5+: -m620} \
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%{mcpu=powerpc: -mppc} \
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%{mcpu=rs64a: -mppc} \
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%{mcpu=603: -m603} \
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@ -94,8 +94,18 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
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builtin_define ("_ARCH_PWR");
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if (TARGET_POWERPC)
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builtin_define ("_ARCH_PPC");
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if (TARGET_PPC_GPOPT)
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builtin_define ("_ARCH_PPCSQ");
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if (TARGET_PPC_GFXOPT)
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builtin_define ("_ARCH_PPCGR");
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if (TARGET_POWERPC64)
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builtin_define ("_ARCH_PPC64");
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if (TARGET_MFCRF)
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builtin_define ("_ARCH_PWR4");
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if (TARGET_POPCNTB)
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builtin_define ("_ARCH_PWR5");
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if (TARGET_FPRND)
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builtin_define ("_ARCH_PWR5X");
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if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
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builtin_define ("_ARCH_COM");
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if (TARGET_ALTIVEC)
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@ -1152,6 +1152,9 @@ rs6000_override_options (const char *default_cpu)
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{"power5", PROCESSOR_POWER5,
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POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
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| MASK_MFCRF | MASK_POPCNTB},
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{"power5+", PROCESSOR_POWER5,
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POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
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| MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
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{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
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{"powerpc64", PROCESSOR_POWERPC64,
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POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
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@ -1177,7 +1180,7 @@ rs6000_override_options (const char *default_cpu)
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POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
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POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
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| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
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| MASK_MFCRF)
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| MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
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};
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rs6000_init_hard_regno_mode_ok ();
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@ -72,6 +72,7 @@
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%{mcpu=power3: -mppc64} \
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%{mcpu=power4: -mpower4} \
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%{mcpu=power5: -mpower4} \
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%{mcpu=power5+: -mpower4} \
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%{mcpu=powerpc: -mppc} \
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%{mcpu=rios: -mpwr} \
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%{mcpu=rios1: -mpwr} \
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@ -151,6 +152,14 @@
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#define TARGET_POPCNTB 0
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#endif
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/* Define TARGET_FPRND if the target assembler does not support the
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fp rounding instructions. */
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#ifndef HAVE_AS_FPRND
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#undef TARGET_FPRND
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#define TARGET_FPRND 0
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#endif
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#ifndef TARGET_SECURE_PLT
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#define TARGET_SECURE_PLT 0
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#endif
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@ -34,6 +34,10 @@
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(UNSPEC_MOVSI_GOT 8)
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(UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
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(UNSPEC_FCTIWZ 10)
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(UNSPEC_FRIM 11)
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(UNSPEC_FRIN 12)
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(UNSPEC_FRIP 13)
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(UNSPEC_FRIZ 14)
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(UNSPEC_LD_MPIC 15) ; load_macho_picbase
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(UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
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(UNSPEC_TLSGD 17)
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@ -5317,6 +5321,62 @@
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"{fcirz|fctiwz} %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "btruncdf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"friz %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "btruncsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frizs %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "ceildf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frip %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "ceilsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frips %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "floordf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frim %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "floorsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frims %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "rounddf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frin %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "roundsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frins %0,%1"
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[(set_attr "type" "fp")])
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; An UNSPEC is used so we don't have to support SImode in FP registers.
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(define_insn "stfiwx"
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[(set (match_operand:SI 0 "memory_operand" "=Z")
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@ -54,11 +54,15 @@ Use PowerPC Graphics group optional instructions
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mmfcrf
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Target Report Mask(MFCRF)
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Generate single field mfcr instruction
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Use PowerPC V2.01 single field mfcr instruction
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mpopcntb
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Target Report Mask(POPCNTB)
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Use PowerPC/AS popcntb instruction
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Use PowerPC V2.02 popcntb instruction
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mfprnd
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Target Report Mask(FPRND)
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Use PowerPC V2.02 floating point rounding instructions
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maltivec
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Target Report Mask(ALTIVEC)
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46
gcc/configure
vendored
46
gcc/configure
vendored
@ -15574,6 +15574,52 @@ cat >>confdefs.h <<\_ACEOF
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#define HAVE_AS_POPCNTB 1
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_ACEOF
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fi
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case $target in
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*-*-aix*) conftest_s=' .machine "pwr5x"
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.csect .text[PR]
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frin 1,1';;
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*) conftest_s=' .machine power5x
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.text
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frin 1,1';;
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esac
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echo "$as_me:$LINENO: checking assembler for fp round support" >&5
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echo $ECHO_N "checking assembler for fp round support... $ECHO_C" >&6
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if test "${gcc_cv_as_powerpc_fprnd+set}" = set; then
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echo $ECHO_N "(cached) $ECHO_C" >&6
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else
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gcc_cv_as_powerpc_fprnd=no
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if test $in_tree_gas = yes; then
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if test $gcc_cv_gas_vers -ge `expr \( \( 2 \* 1000 \) + 17 \) \* 1000 + 0`
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then gcc_cv_as_powerpc_fprnd=yes
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fi
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elif test x$gcc_cv_as != x; then
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echo "$conftest_s" > conftest.s
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if { ac_try='$gcc_cv_as -o conftest.o conftest.s >&5'
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{ (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
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(eval $ac_try) 2>&5
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ac_status=$?
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echo "$as_me:$LINENO: \$? = $ac_status" >&5
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(exit $ac_status); }; }
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then
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gcc_cv_as_powerpc_fprnd=yes
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else
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echo "configure: failed program was" >&5
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cat conftest.s >&5
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fi
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rm -f conftest.o conftest.s
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fi
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fi
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echo "$as_me:$LINENO: result: $gcc_cv_as_powerpc_fprnd" >&5
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echo "${ECHO_T}$gcc_cv_as_powerpc_fprnd" >&6
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if test $gcc_cv_as_powerpc_fprnd = yes; then
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cat >>confdefs.h <<\_ACEOF
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#define HAVE_AS_FPRND 1
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_ACEOF
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fi
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case $target in
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@ -2762,6 +2762,21 @@ foo: nop
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[AC_DEFINE(HAVE_AS_POPCNTB, 1,
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[Define if your assembler supports popcntb field.])])
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case $target in
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*-*-aix*) conftest_s=' .machine "pwr5x"
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.csect .text[[PR]]
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frin 1,1';;
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*) conftest_s=' .machine power5x
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.text
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frin 1,1';;
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esac
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gcc_GAS_CHECK_FEATURE([fp round support],
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gcc_cv_as_powerpc_fprnd, [2,17,0],,
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[$conftest_s],,
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[AC_DEFINE(HAVE_AS_FPRND, 1,
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[Define if your assembler supports fprnd.])])
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case $target in
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*-*-aix*) conftest_s=' .csect .text[[PR]]
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LCF..0:
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@ -636,6 +636,7 @@ See RS/6000 and PowerPC Options.
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-maltivec -mno-altivec @gol
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-mpowerpc-gpopt -mno-powerpc-gpopt @gol
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-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
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-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mfprnd -mno-fprnd @gol
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-mnew-mnemonics -mold-mnemonics @gol
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-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
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-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
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@ -10830,6 +10831,12 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
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@itemx -mno-powerpc-gfxopt
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@itemx -mpowerpc64
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@itemx -mno-powerpc64
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@itemx -mmfcrf
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@itemx -mno-mfcrf
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@itemx -mpopcntb
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@itemx -mno-popcntb
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@itemx -mfprnd
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@itemx -mno-fprnd
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@opindex mpower
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@opindex mno-power
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@opindex mpower2
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@ -10842,12 +10849,18 @@ These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
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@opindex mno-powerpc-gfxopt
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@opindex mpowerpc64
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@opindex mno-powerpc64
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@opindex mmfcrf
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@opindex mno-mfcrf
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@opindex mpopcntb
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@opindex mno-popcntb
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@opindex mfprnd
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@opindex mno-fprnd
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GCC supports two related instruction set architectures for the
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RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
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instructions supported by the @samp{rios} chip set used in the original
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RS/6000 systems and the @dfn{PowerPC} instruction set is the
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architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
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the IBM 4xx microprocessors.
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architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
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the IBM 4xx, 6xx, and follow-on microprocessors.
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Neither architecture is a subset of the other. However there is a
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large common subset of instructions supported by both. An MQ
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@ -10875,6 +10888,18 @@ General Purpose group, including floating-point square root. Specifying
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use the optional PowerPC architecture instructions in the Graphics
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group, including floating-point select.
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The @option{-mmfcrf} option allows GCC to generate the move from
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condition register field instruction implemented on the POWER4
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processor and other processors that support the PowerPC V2.01
|
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architecture.
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The @option{-mpopcntb} option allows GCC to generate the popcount and
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double precision FP reciprocal estimate instruction implemented on the
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POWER5 processor and other processors that support the PowerPC V2.02
|
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architecture.
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The @option{-mfprnd} option allows GCC to generate the FP round to
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integer instructions implemented on the POWER5+ processor and other
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processors that support the PowerPC V2.03 architecture.
|
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|
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The @option{-mpowerpc64} option allows GCC to generate the additional
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64-bit instructions that are found in the full PowerPC64 architecture
|
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and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
|
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@ -10913,9 +10938,10 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
|
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@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
|
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@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
|
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@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
|
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@samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
|
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@samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3},
|
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@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
|
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@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
|
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@samp{power4}, @samp{power5}, @samp{power5+},
|
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@samp{common}, @samp{powerpc}, @samp{powerpc64},
|
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@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
|
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|
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@option{-mcpu=common} selects a completely generic processor. Code
|
||||
@ -10935,19 +10961,20 @@ those options will run best on that processor, and may not run at all on
|
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others.
|
||||
|
||||
The @option{-mcpu} options automatically enable or disable the
|
||||
following options: @option{-maltivec}, @option{-mhard-float},
|
||||
@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
|
||||
@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
|
||||
@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
|
||||
@option{-mstring}. The particular options set for any particular CPU
|
||||
will vary between compiler versions, depending on what setting seems
|
||||
to produce optimal code for that CPU; it doesn't necessarily reflect
|
||||
the actual hardware's capabilities. If you wish to set an individual
|
||||
option to a particular value, you may specify it after the
|
||||
@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
|
||||
following options: @option{-maltivec}, @option{-mfprnd},
|
||||
@option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
|
||||
@option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
|
||||
@option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
|
||||
@option{-mpowerpc-gfxopt}, @option{-mstring}. The particular options
|
||||
set for any particular CPU will vary between compiler versions,
|
||||
depending on what setting seems to produce optimal code for that CPU;
|
||||
it doesn't necessarily reflect the actual hardware's capabilities. If
|
||||
you wish to set an individual option to a particular value, you may
|
||||
specify it after the @option{-mcpu} option, like @samp{-mcpu=970
|
||||
-mno-altivec}.
|
||||
|
||||
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
|
||||
not enabled or disabled by the @option{-mcpu} option at present, since
|
||||
not enabled or disabled by the @option{-mcpu} option at present because
|
||||
AIX does not have full support for these options. You may still
|
||||
enable or disable them individually if you're sure it'll work in your
|
||||
environment.
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user