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mips.h (ISA_HAS_BBIT): New macro.
* config/mips/mips.h (ISA_HAS_BBIT): New macro. * config/mips/mips.md (branch_likely): Remove const. Fix comment formatting. (define_delay for type "branch"): Change to only apply for branch with likely variant. (define_delay for type "branch" and "branch_likely" no). New delay definition. (equality_op): New code iterator. (bbv, bbinv): New code attributes. (*branch_bit<bbv><mode>, *branch_bit<bbv><mode>_inverted): New patterns. testsuite/ * gcc.target/mips/octeon-bbit-1.c: New test. * gcc.target/mips/octeon-bbit-2.c: New test. * gcc.target/mips/octeon-bbit-3.c: New test. From-SVN: r139743
This commit is contained in:
Adam Nemet
Adam Nemet
parent
528c22f4c7
commit
95f6fc6090
gcc
@ -1,3 +1,17 @@
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2008-08-28 Adam Nemet <anemet@caviumnetworks.com>
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* config/mips/mips.h (ISA_HAS_BBIT): New macro.
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* config/mips/mips.md (branch_likely): Remove const. Fix
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comment formatting.
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(define_delay for type "branch"): Change to only apply for branch
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with likely variant.
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(define_delay for type "branch" and "branch_likely" no). New delay
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definition.
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(equality_op): New code iterator.
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(bbv, bbinv): New code attributes.
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(*branch_bit<bbv><mode>, *branch_bit<bbv><mode>_inverted): New
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patterns.
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2008-08-28 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
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Andrew Pinski <pinskia@gcc.gnu.org>
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@ -1006,6 +1006,9 @@ enum mips_code_readable_setting {
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? TARGET_LLSC && !TARGET_MIPS16 \
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: ISA_HAS_LL_SC)
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/* ISA includes the bbit* instructions. */
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#define ISA_HAS_BBIT TARGET_OCTEON
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/* ISA includes the pop instruction. */
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#define ISA_HAS_POP TARGET_OCTEON
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@ -599,12 +599,12 @@
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(const_string "yes")
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(const_string "no")))
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;; Attribute defining whether or not we can use the branch-likely instructions
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;; Attribute defining whether or not we can use the branch-likely
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;; instructions.
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(define_attr "branch_likely" "no,yes"
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(const
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(if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
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(const_string "yes")
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(const_string "no"))))
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(if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
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(const_string "yes")
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(const_string "no")))
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;; True if an instruction might assign to hi or lo when reloaded.
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;; This is used by the TUNE_MACC_CHAINS code.
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@ -788,6 +788,9 @@
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;; by swapping the operands.
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(define_code_iterator swapped_fcond [ge gt unge ungt])
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;; Equality operators.
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(define_code_iterator equality_op [eq ne])
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;; These code iterators allow the signed and unsigned scc operations to use
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;; the same template.
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(define_code_iterator any_gt [gt gtu])
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@ -848,6 +851,12 @@
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(unge "ule")
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(ungt "ult")])
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;; The value of the bit when the branch is taken for branch_bit patterns.
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;; Comparison is always against zero so this depends on the operator.
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(define_code_attr bbv [(eq "0") (ne "1")])
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;; This is the inverse value of bbv.
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(define_code_attr bbinv [(eq "1") (ne "0")])
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;; .........................
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;;
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@ -856,11 +865,19 @@
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;; .........................
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(define_delay (and (eq_attr "type" "branch")
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(eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
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(eq (symbol_ref "TARGET_MIPS16") (const_int 0))
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(eq_attr "branch_likely" "yes"))
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[(eq_attr "can_delay" "yes")
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(nil)
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(and (eq_attr "branch_likely" "yes")
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(eq_attr "can_delay" "yes"))])
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(eq_attr "can_delay" "yes")])
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;; Branches that don't have likely variants do not annul on false.
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(define_delay (and (eq_attr "type" "branch")
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(eq (symbol_ref "TARGET_MIPS16") (const_int 0))
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(eq_attr "branch_likely" "no"))
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[(eq_attr "can_delay" "yes")
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(nil)
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(nil)])
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(define_delay (eq_attr "type" "jump")
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[(eq_attr "can_delay" "yes")
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@ -5052,6 +5069,50 @@
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(if_then_else (match_operand 0)
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(label_ref (match_operand 1))
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(pc)))])
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;; Branch if bit is set/clear.
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(define_insn "*branch_bit<bbv><mode>"
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[(set (pc)
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(if_then_else
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(equality_op (zero_extract:GPR
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(match_operand:GPR 1 "register_operand" "d")
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(const_int 1)
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(match_operand 2 "const_int_operand" ""))
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(const_int 0))
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(label_ref (match_operand 0 ""))
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(pc)))]
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"ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
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{
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return
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mips_output_conditional_branch (insn, operands,
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MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
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MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
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}
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[(set_attr "type" "branch")
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(set_attr "mode" "none")
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(set_attr "branch_likely" "no")])
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(define_insn "*branch_bit<bbv><mode>_inverted"
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[(set (pc)
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(if_then_else
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(equality_op (zero_extract:GPR
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(match_operand:GPR 1 "register_operand" "d")
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(const_int 1)
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(match_operand 2 "const_int_operand" ""))
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(const_int 0))
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(pc)
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(label_ref (match_operand 0 ""))))]
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"ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
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{
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return
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mips_output_conditional_branch (insn, operands,
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MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
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MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
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}
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[(set_attr "type" "branch")
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(set_attr "mode" "none")
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(set_attr "branch_likely" "no")])
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;;
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;; ....................
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@ -1,3 +1,9 @@
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2008-08-28 Adam Nemet <anemet@caviumnetworks.com>
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* gcc.target/mips/octeon-bbit-1.c: New test.
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* gcc.target/mips/octeon-bbit-2.c: New test.
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* gcc.target/mips/octeon-bbit-3.c: New test.
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2008-08-28 Manuel Lopez-Ibanez <manu@gcc.gnu.org>
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Andrew Pinski <pinskia@gcc.gnu.org>
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55
gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
Normal file
55
gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
Normal file
@ -0,0 +1,55 @@
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/* { dg-do compile } */
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/* { dg-mips-options "-O2 -march=octeon" } */
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/* { dg-final { scan-assembler-times "\tbbit1\t" 4 } } */
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/* { dg-final { scan-assembler-times "\tbbit0\t" 2 } } */
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/* { dg-final { scan-assembler-not "andi\t" } } */
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NOMIPS16 void
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f1 (long long i)
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{
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if (i & 0x80)
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foo ();
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}
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NOMIPS16 void
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f2 (int i)
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{
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if (!(i & 0x80))
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foo ();
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}
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NOMIPS16 void
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f3 (int i)
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{
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if (i % 2)
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foo ();
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}
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NOMIPS16 void
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f4 (int i)
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{
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if (i & 1)
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foo ();
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}
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NOMIPS16 void
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f5 (long long i)
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{
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if ((i >> 3) & 1)
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foo ();
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}
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unsigned long long r;
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NOMIPS16 static inline __attribute__((always_inline)) int
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test_bit(unsigned long long nr, const unsigned long long *addr)
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{
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return 1UL & (addr[nr >> 6] >> (nr & 63ULL));
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}
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NOMIPS16 void
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f6 ()
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{
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if (!test_bit(0, &r))
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g ();
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}
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24
gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
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24
gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
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/* { dg-do compile } */
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/* { dg-mips-options "-O2 -march=octeon -mbranch-likely" } */
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/* { dg-final { scan-assembler "\tbbit\[01\]\t" } } */
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/* { dg-final { scan-assembler-not "\tbbit\[01\]l\t" } } */
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/* { dg-final { scan-assembler "\tbnel\t" } } */
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/* { dg-final { scan-assembler-not "\tbne\t" } } */
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NOMIPS16 int
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f (int n, int i)
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{
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int s = 0;
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for (; i & 1; i++)
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s += i;
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return s;
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}
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NOMIPS16 int
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g (int n, int i)
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{
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int s = 0;
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for (i = 0; i < n; i++)
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s += i;
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return s;
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}
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31
gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
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31
gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
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@ -0,0 +1,31 @@
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/* { dg-do compile } */
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/* { dg-mips-options "-O2 -march=octeon" } */
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/* { dg-final { scan-assembler-times "\tbbit\[01\]\t|\tbgez\t" 2 } } */
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/* { dg-final { scan-assembler-not "ext\t" } } */
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void abort (void);
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void exit (int);
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typedef unsigned long long ulong64;
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typedef struct bitfield_s {
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ulong64 a:1;
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ulong64 b:29;
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ulong64 c:1;
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ulong64 d:15;
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ulong64 f:18;
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} bitfield_t;
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bitfield_t bar;
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NOMIPS16 void
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f ()
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{
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foo(&bar);
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if (bar.a != 0x1)
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abort ();
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else if (!bar.c)
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abort ();
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else
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exit (0);
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}
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