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i386.md (plogic): New.
2008-04-02 H.J. Lu <hongjiu.lu@intel.com> * config/i386/i386.md (plogic): New. (plogicprefix): Likewise. * config/i386/mmx.md (mmx_<code><mode>3): New. (mmx_and<mode>3): Removed. (mmx_ior<mode>3): Likewise. (mmx_xor<mode>3): Likewise. * config/i386/sse.md (<code><mode>3): New. (*<code><mode>3): Likewise. (*<code><mode>3): Likewise. (<code><mode>3): Likewise. (*sse_<code><mode>3): Likewise. (*sse2_<code><mode>3): Likewise. (<code>tf3): Likewise. (*<code>tf3): Likewise. (and<mode>3): Likewise. (*and<mode>3): Likewise. (ior<mode>3): Removed. (*ior<mode>3): Likewise. (xor<mode>3): Likewise. (*xor<mode>3): Likewise. (*and<mode>3): Likewise. (*ior<mode>3): Likewise. (*xor<mode>3): Likewise. (and<mode>3): Likewise. (*sse_and<mode>3): Likewise. (*sse2_and<mode>3): Likewise. (andtf3): Likewise. (*andtf3): Likewise. (ior<mode>3): Likewise. (*sse_ior<mode>3): Likewise. (*sse2_ior<mode>3): Likewise. (iortf3): Likewise. (*iortf3): Likewise. (xor<mode>3): Likewise. (*sse_xor<mode>3): Likewise. (*sse2_xor<mode>3): Likewise. (xortf3): Likewise. (*xortf3): Likewise. From-SVN: r133837
This commit is contained in:
H.J. Lu
H.J. Lu
parent
b7814a183c
commit
94237c92ef
@ -1,3 +1,46 @@
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2008-04-02 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/i386.md (plogic): New.
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(plogicprefix): Likewise.
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* config/i386/mmx.md (mmx_<code><mode>3): New.
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(mmx_and<mode>3): Removed.
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(mmx_ior<mode>3): Likewise.
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(mmx_xor<mode>3): Likewise.
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* config/i386/sse.md (<code><mode>3): New.
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(*<code><mode>3): Likewise.
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(*<code><mode>3): Likewise.
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(<code><mode>3): Likewise.
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(*sse_<code><mode>3): Likewise.
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(*sse2_<code><mode>3): Likewise.
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(<code>tf3): Likewise.
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(*<code>tf3): Likewise.
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(and<mode>3): Likewise.
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(*and<mode>3): Likewise.
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(ior<mode>3): Removed.
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(*ior<mode>3): Likewise.
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(xor<mode>3): Likewise.
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(*xor<mode>3): Likewise.
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(*and<mode>3): Likewise.
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(*ior<mode>3): Likewise.
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(*xor<mode>3): Likewise.
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(and<mode>3): Likewise.
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(*sse_and<mode>3): Likewise.
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(*sse2_and<mode>3): Likewise.
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(andtf3): Likewise.
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(*andtf3): Likewise.
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(ior<mode>3): Likewise.
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(*sse_ior<mode>3): Likewise.
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(*sse2_ior<mode>3): Likewise.
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(iortf3): Likewise.
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(*iortf3): Likewise.
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(xor<mode>3): Likewise.
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(*sse_xor<mode>3): Likewise.
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(*sse2_xor<mode>3): Likewise.
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(xortf3): Likewise.
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(*xortf3): Likewise.
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2008-04-02 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/14495
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@ -540,6 +540,12 @@
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(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
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(define_code_attr maxminfprefix [(smax "max") (smin "min")])
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;; Mapping of parallel logic operators
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(define_code_iterator plogic [and ior xor])
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;; Base name for insn mnemonic.
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(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])
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;; All single word integer modes.
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(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
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@ -791,16 +791,6 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn "mmx_and<mode>3"
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[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
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(and:MMXMODEI
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(match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
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"TARGET_MMX && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
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"pand\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "DI")])
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(define_insn "mmx_nand<mode>3"
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[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
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(and:MMXMODEI
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@ -811,27 +801,16 @@
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "DI")])
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(define_insn "mmx_ior<mode>3"
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(define_insn "mmx_<code><mode>3"
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[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
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(ior:MMXMODEI
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(plogic:MMXMODEI
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(match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
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"TARGET_MMX && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
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"por\t{%2, %0|%0, %2}"
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"TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"p<plogicprefix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "DI")])
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(define_insn "mmx_xor<mode>3"
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[(set (match_operand:MMXMODEI 0 "register_operand" "=y")
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(xor:MMXMODEI
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(match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
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"TARGET_MMX && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
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"pxor\t{%2, %0|%0, %2}"
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[(set_attr "type" "mmxadd")
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(set_attr "mode" "DI")
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(set_attr "memory" "none")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel integral element swizzling
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@ -839,25 +839,6 @@
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_expand "and<mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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(and:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
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(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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"ix86_fixup_binary_operands_no_copy (AND, <MODE>mode, operands);")
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(define_insn "*and<mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
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(and:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
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&& ix86_binary_operator_ok (AND, <MODE>mode, operands)"
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"andp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "<MODE>")])
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(define_insn "<sse>_nand<mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
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(and:SSEMODEF2P
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@ -869,41 +850,22 @@
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[(set_attr "type" "sselog")
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(set_attr "mode" "<MODE>")])
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(define_expand "ior<mode>3"
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(define_expand "<code><mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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(ior:SSEMODEF2P
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(plogic:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
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(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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"ix86_fixup_binary_operands_no_copy (IOR, <MODE>mode, operands);")
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"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
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(define_insn "*ior<mode>3"
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(define_insn "*<code><mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
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(ior:SSEMODEF2P
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(plogic:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
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&& ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
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"orp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "<MODE>")])
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(define_expand "xor<mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "")
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(xor:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
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(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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"ix86_fixup_binary_operands_no_copy (XOR, <MODE>mode, operands);")
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(define_insn "*xor<mode>3"
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[(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
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(xor:SSEMODEF2P
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(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)
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&& ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
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"xorp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
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&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"<plogicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "<MODE>")])
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@ -912,16 +874,6 @@
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;; allocation lossage. These patterns do not allow memory operands
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;; because the native instructions read the full 128-bits.
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(define_insn "*and<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(and:MODEF
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(match_operand:MODEF 1 "register_operand" "0")
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(match_operand:MODEF 2 "register_operand" "x")))]
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"SSE_FLOAT_MODE_P (<MODE>mode)"
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"andp<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "<ssevecmode>")])
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(define_insn "*nand<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(and:MODEF
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@ -933,23 +885,13 @@
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[(set_attr "type" "sselog")
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(set_attr "mode" "<ssevecmode>")])
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(define_insn "*ior<mode>3"
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(define_insn "*<code><mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(ior:MODEF
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(plogic:MODEF
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(match_operand:MODEF 1 "register_operand" "0")
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(match_operand:MODEF 2 "register_operand" "x")))]
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"SSE_FLOAT_MODE_P (<MODE>mode)"
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"orp<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "<ssevecmode>")])
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(define_insn "*xor<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(xor:MODEF
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(match_operand:MODEF 1 "register_operand" "0")
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(match_operand:MODEF 2 "register_operand" "x")))]
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"SSE_FLOAT_MODE_P (<MODE>mode)"
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"xorp<ssemodefsuffix>\t{%2, %0|%0, %2}"
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"<plogicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "<ssevecmode>")])
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@ -3820,35 +3762,6 @@
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operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
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})
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(define_expand "and<mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "")
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(and:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
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"TARGET_SSE"
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"ix86_fixup_binary_operands_no_copy (AND, <MODE>mode, operands);")
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(define_insn "*sse_and<mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
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(and:SSEMODEI
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(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
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"(TARGET_SSE && !TARGET_SSE2)
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&& ix86_binary_operator_ok (AND, <MODE>mode, operands)"
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"andps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "V4SF")])
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(define_insn "*sse2_and<mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
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(and:SSEMODEI
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(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
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"TARGET_SSE2 && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
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"pand\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_insn "*sse_nand<mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
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(and:SSEMODEI
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@ -3870,24 +3783,6 @@
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_expand "andtf3"
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[(set (match_operand:TF 0 "register_operand" "")
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(and:TF (match_operand:TF 1 "nonimmediate_operand" "")
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(match_operand:TF 2 "nonimmediate_operand" "")))]
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"TARGET_64BIT"
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"ix86_fixup_binary_operands_no_copy (AND, TFmode, operands);")
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(define_insn "*andtf3"
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[(set (match_operand:TF 0 "register_operand" "=x")
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(and:TF
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(match_operand:TF 1 "nonimmediate_operand" "%0")
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(match_operand:TF 2 "nonimmediate_operand" "xm")))]
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"TARGET_64BIT && ix86_binary_operator_ok (AND, TFmode, operands)"
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"pand\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_insn "*nandtf3"
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[(set (match_operand:TF 0 "register_operand" "=x")
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(and:TF
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@ -3899,96 +3794,51 @@
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_expand "ior<mode>3"
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(define_expand "<code><mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "")
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(ior:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
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(plogic:SSEMODEI
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(match_operand:SSEMODEI 1 "nonimmediate_operand" "")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
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"TARGET_SSE"
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"ix86_fixup_binary_operands_no_copy (IOR, <MODE>mode, operands);")
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"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
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(define_insn "*sse_ior<mode>3"
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(define_insn "*sse_<code><mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
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(ior:SSEMODEI
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(plogic:SSEMODEI
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(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
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"(TARGET_SSE && !TARGET_SSE2)
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&& ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
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"orps\t{%2, %0|%0, %2}"
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&& ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"<plogicprefix>ps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "mode" "V4SF")])
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(define_insn "*sse2_ior<mode>3"
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(define_insn "*sse2_<code><mode>3"
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[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
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(ior:SSEMODEI
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(plogic:SSEMODEI
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(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
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(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
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"TARGET_SSE2 && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
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"por\t{%2, %0|%0, %2}"
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"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"p<plogicprefix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1")
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(set_attr "mode" "TI")])
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(define_expand "iortf3"
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(define_expand "<code>tf3"
|
||||
[(set (match_operand:TF 0 "register_operand" "")
|
||||
(ior:TF (match_operand:TF 1 "nonimmediate_operand" "")
|
||||
(match_operand:TF 2 "nonimmediate_operand" "")))]
|
||||
(plogic:TF
|
||||
(match_operand:TF 1 "nonimmediate_operand" "")
|
||||
(match_operand:TF 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_64BIT"
|
||||
"ix86_fixup_binary_operands_no_copy (IOR, TFmode, operands);")
|
||||
"ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
|
||||
|
||||
(define_insn "*iortf3"
|
||||
(define_insn "*<code>tf3"
|
||||
[(set (match_operand:TF 0 "register_operand" "=x")
|
||||
(ior:TF
|
||||
(plogic:TF
|
||||
(match_operand:TF 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_64BIT && ix86_binary_operator_ok (IOR, TFmode, operands)"
|
||||
"por\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sselog")
|
||||
(set_attr "prefix_data16" "1")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_expand "xor<mode>3"
|
||||
[(set (match_operand:SSEMODEI 0 "register_operand" "")
|
||||
(xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
|
||||
(match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_SSE"
|
||||
"ix86_fixup_binary_operands_no_copy (XOR, <MODE>mode, operands);")
|
||||
|
||||
(define_insn "*sse_xor<mode>3"
|
||||
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
|
||||
(xor:SSEMODEI
|
||||
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
|
||||
"(TARGET_SSE && !TARGET_SSE2)
|
||||
&& ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
|
||||
"xorps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sselog")
|
||||
(set_attr "mode" "V4SF")])
|
||||
|
||||
(define_insn "*sse2_xor<mode>3"
|
||||
[(set (match_operand:SSEMODEI 0 "register_operand" "=x")
|
||||
(xor:SSEMODEI
|
||||
(match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_SSE2 && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
|
||||
"pxor\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sselog")
|
||||
(set_attr "prefix_data16" "1")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_expand "xortf3"
|
||||
[(set (match_operand:TF 0 "register_operand" "")
|
||||
(xor:TF (match_operand:TF 1 "nonimmediate_operand" "")
|
||||
(match_operand:TF 2 "nonimmediate_operand" "")))]
|
||||
"TARGET_64BIT"
|
||||
"ix86_fixup_binary_operands_no_copy (XOR, TFmode, operands);")
|
||||
|
||||
(define_insn "*xortf3"
|
||||
[(set (match_operand:TF 0 "register_operand" "=x")
|
||||
(xor:TF
|
||||
(match_operand:TF 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:TF 2 "nonimmediate_operand" "xm")))]
|
||||
"TARGET_64BIT && ix86_binary_operator_ok (XOR, TFmode, operands)"
|
||||
"pxor\t{%2, %0|%0, %2}"
|
||||
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
|
||||
"p<plogicprefix>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sselog")
|
||||
(set_attr "prefix_data16" "1")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user