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rs6000.c (rs6000_dbx_register_number): New function.
* config/rs6000/rs6000.c (rs6000_dbx_register_number): New function. * config/rs6000/rs6000-protos.h (rs6000_dbx_register_number): Declare. * config/rs6000/rs6000.h (DWARF_FRAME_REGNUM): Define. (DWARF_REG_TO_UNWIND_COLUMN): Correct column adjustment and comment. * config/rs6000/sysv4.h (DBX_REGISTER_NUMBER): Define. From-SVN: r75497
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Alan Modra
Alan Modra
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deae8de664
commit
93c9d1bae6
@ -1,3 +1,11 @@
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2004-01-07 Alan Modra <amodra@bigpond.net.au>
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* config/rs6000/rs6000.c (rs6000_dbx_register_number): New function.
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* config/rs6000/rs6000-protos.h (rs6000_dbx_register_number): Declare.
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* config/rs6000/rs6000.h (DWARF_FRAME_REGNUM): Define.
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(DWARF_REG_TO_UNWIND_COLUMN): Correct column adjustment and comment.
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* config/rs6000/sysv4.h (DBX_REGISTER_NUMBER): Define.
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2004-01-06 Eric Christopher <echristo@redhat.com>
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* config/mips/mips.h (MDEBUG_ASM_SPEC): Change for dwarf2 default.
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@ -1,5 +1,6 @@
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/* Definitions of target machine for GNU compiler, for IBM RS/6000.
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Copyright (C) 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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Copyright (C) 2000, 2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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This file is part of GCC.
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@ -186,6 +187,7 @@ extern int uses_TOC (void);
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extern void rs6000_emit_prologue (void);
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extern void rs6000_emit_load_toc_table (int);
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extern void rs6000_aix_emit_builtin_unwind_init (void);
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extern unsigned int rs6000_dbx_register_number (unsigned int);
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extern void rs6000_emit_epilogue (int);
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extern void rs6000_emit_eh_reg_restore (rtx, rtx);
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extern const char * output_isel (rtx *);
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@ -1,6 +1,6 @@
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/* Subroutines used for code generation on IBM RS/6000.
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Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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This file is part of GCC.
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@ -15763,4 +15763,39 @@ rs6000_dwarf_register_span (rtx reg)
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gen_rtx_REG (SImode, regno + 1200)));
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}
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/* Map internal gcc register numbers to DWARF2 register numbers. */
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unsigned int
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rs6000_dbx_register_number (unsigned int regno)
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{
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if (regno <= 63 || write_symbols != DWARF2_DEBUG)
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return regno;
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if (regno == MQ_REGNO)
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return 100;
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if (regno == LINK_REGISTER_REGNUM)
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return 108;
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if (regno == COUNT_REGISTER_REGNUM)
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return 109;
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if (CR_REGNO_P (regno))
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return regno - CR0_REGNO + 86;
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if (regno == XER_REGNO)
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return 101;
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if (ALTIVEC_REGNO_P (regno))
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return regno - FIRST_ALTIVEC_REGNO + 1124;
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if (regno == VRSAVE_REGNO)
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return 356;
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if (regno == VSCR_REGNO)
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return 67;
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if (regno == SPE_ACC_REGNO)
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return 99;
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if (regno == SPEFSCR_REGNO)
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return 612;
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/* SPE high reg number. We get these values of regno from
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rs6000_dwarf_register_span. */
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if (regno >= 1200 && regno < 1232)
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return regno;
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abort ();
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}
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#include "gt-rs6000.h"
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@ -1,6 +1,6 @@
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/* Definitions of target machine for GNU compiler, for IBM RS/6000.
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Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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This file is part of GCC.
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@ -811,19 +811,27 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
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/* This must be included for pre gcc 3.0 glibc compatibility. */
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#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
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/* Add 32 dwarf columns for synthetic SPE registers. The SPE
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synthetic registers are 113 through 145. */
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/* Add 32 dwarf columns for synthetic SPE registers. */
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#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
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/* The SPE has an additional 32 synthetic registers starting at 1200.
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We must map them here to sane values in the unwinder to avoid a
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huge hole in the unwind tables.
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/* The SPE has an additional 32 synthetic registers, with DWARF debug
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info numbering for these registers starting at 1200. While eh_frame
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register numbering need not be the same as the debug info numbering,
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we choose to number these regs for eh_frame at 1200 too. This allows
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future versions of the rs6000 backend to add hard registers and
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continue to use the gcc hard register numbering for eh_frame. If the
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extra SPE registers in eh_frame were numbered starting from the
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current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
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changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
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avoid invalidating older SPE eh_frame info.
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FIXME: the AltiVec ABI has AltiVec registers being 1124-1155, and
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the VRSAVE SPR (SPR256) assigned to register 356. When AltiVec EH
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is verified to be working, this macro should be changed
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accordingly. */
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#define DWARF_REG_TO_UNWIND_COLUMN(r) ((r) > 1200 ? ((r) - 1200 + 113) : (r))
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We must map them here to avoid huge unwinder tables mostly consisting
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of unused space. */
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#define DWARF_REG_TO_UNWIND_COLUMN(r) \
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((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
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/* Use gcc hard register numbering for eh_frame. */
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#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator.
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@ -1,6 +1,6 @@
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/* Target definitions for GNU compiler for PowerPC running System V.4
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Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
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2004 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GCC.
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@ -742,6 +742,8 @@ extern int fixuplabelno;
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/* Historically we have also supported stabs debugging. */
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#define DBX_DEBUGGING_INFO 1
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#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
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#define TARGET_ENCODE_SECTION_INFO rs6000_elf_encode_section_info
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#define TARGET_IN_SMALL_DATA_P rs6000_elf_in_small_data_p
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#define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags
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