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alpha.h (enum reg_class): Add PV_REG.
* config/alpha/alpha.h (enum reg_class): Add PV_REG. (REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update. (REG_CLASS_FROM_LETTER): Assign it to 'c'. * config/alpha/alpha.md (call_osf_1): Use it. (call_value_osf_1): Likewise. From-SVN: r37091
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@ -1,5 +1,11 @@
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2000-10-27 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.h (enum reg_class): Add PV_REG.
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(REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGNO_REG_CLASS): Update.
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(REG_CLASS_FROM_LETTER): Assign it to 'c'.
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* config/alpha/alpha.md (call_osf_1): Use it.
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(call_value_osf_1): Likewise.
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* config/ia64/ia64.c: Revert 10-23 patch.
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(ia64_hard_regno_rename_ok): New.
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* config/ia64/ia64-protos.h: Declare it.
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@ -719,7 +719,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
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For any two classes, it is very desirable that there be another
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class that represents their union. */
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enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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enum reg_class { NO_REGS, PV_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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LIM_REG_CLASSES };
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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@ -727,22 +727,24 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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/* Give names of register classes as strings for dump file. */
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#define REG_CLASS_NAMES \
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{"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
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{"NO_REGS", "PV_REG", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
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/* Define which registers fit in which classes.
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This is an initializer for a vector of HARD_REG_SET
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of length N_REG_CLASSES. */
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#define REG_CLASS_CONTENTS \
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{ {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
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{ {0, 0}, {0x08000000, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
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/* The same information, inverted:
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Return the class number of the smallest class containing
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reg number REGNO. This could be a conditional expression
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or could index an array. */
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
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#define REGNO_REG_CLASS(REGNO) \
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((REGNO) == 27 ? PV_REG \
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: (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
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: GENERAL_REGS)
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/* The class value for index registers, and the one for base regs. */
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#define INDEX_REG_CLASS NO_REGS
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@ -751,7 +753,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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/* Get reg_class from a letter such as appears in the machine description. */
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#define REG_CLASS_FROM_LETTER(C) \
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((C) == 'f' ? FLOAT_REGS : NO_REGS)
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((C) == 'c' ? PV_REG : (C) == 'f' ? FLOAT_REGS : NO_REGS)
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/* Define this macro to change register usage conditional on target flags. */
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/* #define CONDITIONAL_REGISTER_USAGE */
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@ -4223,7 +4223,7 @@
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}")
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(define_insn "*call_osf_1"
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[(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
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[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,i"))
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(match_operand 1 "" ""))
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(clobber (reg:DI 27))
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(clobber (reg:DI 26))]
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@ -5976,7 +5976,7 @@
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(define_insn "*call_value_osf_1"
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[(set (match_operand 0 "" "")
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(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
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(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,i"))
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(match_operand 2 "" "")))
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(clobber (reg:DI 27))
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(clobber (reg:DI 26))]
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