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vector.md (vec_unpacks_hi_v4sf): Correct for endianness.

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2013-10-16  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for
	endianness.
	(vec_unpacks_lo_v4sf): Likewise.
	(vec_unpacks_float_hi_v4si): Likewise.
	(vec_unpacks_float_lo_v4si): Likewise.
	(vec_unpacku_float_hi_v4si): Likewise.
	(vec_unpacku_float_lo_v4si): Likewise.

From-SVN: r203714
This commit is contained in:
Bill Schmidt 2013-10-16 17:56:22 +00:00 committed by William Schmidt
parent de75c8761e
commit 90d3bd5106
2 changed files with 16 additions and 6 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc/config/rs6000/vector.md (vec_unpacks_hi_v4sf): Correct for
endianness.
(vec_unpacks_lo_v4sf): Likewise.
(vec_unpacks_float_hi_v4si): Likewise.
(vec_unpacks_float_lo_v4si): Likewise.
(vec_unpacku_float_hi_v4si): Likewise.
(vec_unpacku_float_lo_v4si): Likewise.
2013-10-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_concat_<mode>): Adjust output for LE.

12
gcc/config/rs6000/vector.md
View File

@ -872,7 +872,7 @@
{
rtx reg = gen_reg_rtx (V4SFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], true);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
DONE;
})
@ -884,7 +884,7 @@
{
rtx reg = gen_reg_rtx (V4SFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], false);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
DONE;
})
@ -896,7 +896,7 @@
{
rtx reg = gen_reg_rtx (V4SImode);
rs6000_expand_interleave (reg, operands[1], operands[1], true);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
DONE;
})
@ -908,7 +908,7 @@
{
rtx reg = gen_reg_rtx (V4SImode);
rs6000_expand_interleave (reg, operands[1], operands[1], false);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
DONE;
})
@ -920,7 +920,7 @@
{
rtx reg = gen_reg_rtx (V4SImode);
rs6000_expand_interleave (reg, operands[1], operands[1], true);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
DONE;
})
@ -932,7 +932,7 @@
{
rtx reg = gen_reg_rtx (V4SImode);
rs6000_expand_interleave (reg, operands[1], operands[1], false);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
DONE;
})