re PR rtl-optimization/45652 (gcc.dg/compat/scalar-by-value-3 FAILs with -O2 -fselective-scheduling2)

PR rtl-optimization/45652
	* alias.c (get_reg_base_value): New.
	* rtl.h (get_reg_base_value): Add prototype.
	* sel-sched.c (init_regs_for_mode): Use it.  Don't use registers with
	non-null REG_BASE_VALUE for renaming.

testsuite:
	* gcc.dg/pr45652.c: New.

From-SVN: r167025

gcc/ChangeLog

@@ -1,3 +1,10 @@
+2010-11-22  Alexander Monakov  <amonakov@ispras.ru>
+
+	PR rtl-optimization/45652
+	* alias.c (get_reg_base_value): New.
+	* rtl.h (get_reg_base_value): Add prototype.
+	* sel-sched.c (init_regs_for_mode): Use it.  Don't use registers with
+	non-null REG_BASE_VALUE for renaming.
 
 2010-11-22  Jeremie Salvucci  <jeremie.salvucci@free.fr>
 	    Basile Starynkevitch  <basile@starynkevitch.net>

gcc/alias.c

@@ -1291,6 +1291,14 @@ record_set (rtx dest, const_rtx set, void *data ATTRIBUTE_UNUSED)
   reg_seen[regno] = 1;
 }
 
+/* Return REG_BASE_VALUE for REGNO.  Selective scheduler uses this to avoid
+   using hard registers with non-null REG_BASE_VALUE for renaming.  */
+rtx
+get_reg_base_value (unsigned int regno)
+{
+  return VEC_index (rtx, reg_base_value, regno);
+}
+
 /* If a value is known for REGNO, return it.  */
 
 rtx

gcc/rtl.h

@@ -2510,6 +2510,7 @@ extern rtx find_base_term (rtx);
 extern rtx gen_hard_reg_clobber (enum machine_mode, unsigned int);
 extern rtx get_reg_known_value (unsigned int);
 extern bool get_reg_known_equiv_p (unsigned int);
+extern rtx get_reg_base_value (unsigned int);
 
 #ifdef STACK_REGS
 extern int stack_regs_mentioned (const_rtx insn);

gcc/sel-sched.c

@@ -1139,6 +1139,9 @@ init_regs_for_mode (enum machine_mode mode)
             /* Can't use regs which aren't saved by
                the prologue.  */
             || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
+	    /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
+	       it affects aliasing globally and invalidates all AV sets.  */
+	    || get_reg_base_value (cur_reg + i)
 #ifdef LEAF_REGISTERS
             /* We can't use a non-leaf register if we're in a
                leaf function.  */

gcc/testsuite/ChangeLog

@@ -1,3 +1,8 @@
+2010-11-22  Alexander Monakov  <amonakov@ispras.ru>
+
+	PR rtl-optimization/45652
+	* gcc.dg/pr45652.c: New.
+
 2010-11-21  Richard Henderson  <rth@redhat.com>
 
 	PR rtl-optimization/46571

gcc/testsuite/gcc.dg/pr45652.c

@@ -0,0 +1,39 @@
+/* { dg-do run { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -fselective-scheduling2" } */
+
+struct S {
+  double i[2];
+};
+
+void __attribute__ ((noinline)) checkcd (struct S x)
+{
+  if (x.i[0] != 7.0 || x.i[1] != 8.0)
+    __builtin_abort ();
+}
+
+void __attribute__ ((noinline)) testvacd (int n, ...)
+{
+  int i;
+  __builtin_va_list ap;
+  __builtin_va_start (ap, n);
+  for (i = 0; i < n; i++)
+    {
+      struct S t = __builtin_va_arg (ap, struct S);
+      checkcd (t);
+    }
+  __builtin_va_end (ap);
+}
+
+void
+testitcd (void)
+{
+  struct S x = { { 7.0, 8.0 } };
+  testvacd (2, x, x);
+}
+
+int
+main ()
+{
+  testitcd ();
+  return 0;
+}