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i386.md (zero_extend?i?i2): Rewrite to expanders; new patterns rewrite splitters.
* i386.md (zero_extend?i?i2): Rewrite to expanders; new patterns rewrite splitters. From-SVN: r30740
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
b5b8a0e779
commit
8f7661f2b8
@ -1,5 +1,8 @@
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Tue Nov 30 15:20:52 MET 1999 Jan Hubicka <hubicka@freesoft.cz>
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* i386.md (zero_extend?i?i2): Rewrite to expanders; new patterns,
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rewrite splitters.
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* i386.md (neg?f2_if): Split "r" and "f" to separate alternatives.
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(abs?f2_if): Likewise.
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@ -2167,172 +2167,176 @@
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;; Zero extension instructions
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(define_insn "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "=r,?r")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,rm")))
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(clobber (reg:CC 17))]
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(define_expand "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
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""
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"*
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"
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{
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switch (get_attr_type (insn))
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if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
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{
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case TYPE_ALU1:
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if (!REG_P (operands[1]) || REGNO (operands[0]) != REGNO (operands[1]))
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abort ();
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operands[1] = GEN_INT (0xffff);
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return \"and{l}\\t{%1, %0|%0, %1}\";
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default:
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return \"movz{wl|x}\\t{%1, %0|%0, %1}\";
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operands[1] = force_reg (HImode, operands[1]);
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emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
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DONE;
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}
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}"
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[(set (attr "type")
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(if_then_else (and (eq_attr "alternative" "0")
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(ne (symbol_ref "TARGET_ZERO_EXTEND_WITH_AND")
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(const_int 0)))
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(const_string "alu1")
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(const_string "imovx")))])
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}")
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(define_insn "zero_extendhisi2_and"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
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(clobber (reg:CC 17))]
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"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
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"#"
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[(set_attr "type" "alu1")])
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))
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(zero_extend:SI (match_operand:HI 1 "register_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& !reg_overlap_mentioned_p (operands[0], operands[1])"
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[(parallel [(set (match_dup 0) (const_int 0))
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(clobber (reg:CC 17))])
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(set (strict_low_part (subreg:HI (match_dup 0) 0)) (match_dup 1))]
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"")
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:HI 1 "memory_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& reg_overlap_mentioned_p (operands[0], operands[1])"
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[(set (strict_low_part (subreg:HI (match_dup 0) 0)) (match_dup 1))
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(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
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"reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
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[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
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(clobber (reg:CC 17))])]
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"")
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(define_insn "zero_extendqihi2"
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[(set (match_operand:HI 0 "register_operand" "=q,r,r")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0,qm")))
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(clobber (reg:CC 17))]
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""
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_ALU1:
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if (!REG_P (operands[1]) || REGNO (operands[0]) != REGNO (operands[1]))
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abort ();
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operands[1] = GEN_INT (0xff);
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return \"and{l}\\t{%1, %k0|%k0, %1}\";
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default:
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return \"movz{bw|x}\\t{%1, %0|%0, %1}\";
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}
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}"
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[(set (attr "type")
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(cond [(and (eq_attr "alternative" "0")
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(ne (symbol_ref "TARGET_ZERO_EXTEND_WITH_AND")
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(const_int 0)))
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(const_string "alu1")
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(eq_attr "alternative" "1")
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(const_string "alu1")
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]
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(const_string "imovx")))])
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(define_insn "*zero_extendhisi2_movzwl"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
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"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
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"movz{wl|x}\\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx")])
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(define_expand "zero_extendqihi2"
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[(parallel
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC 17))])]
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""
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"")
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(define_insn "*zero_extendqihi2_and"
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[(set (match_operand:HI 0 "register_operand" "=r,?&q")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
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(clobber (reg:CC 17))]
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"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
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"#"
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[(set_attr "type" "alu1")])
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(define_insn "*zero_extendqihi2_movzbw_and"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
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(clobber (reg:CC 17))]
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"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
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"#"
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[(set_attr "type" "imovx,alu1")])
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(define_insn "*zero_extendqihi2_movzbw"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
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"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
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"movz{bw|x}\\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx")])
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;; For the movzbw case strip only the clobber
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(define_split
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
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&& (!REG_P (operands[1]) || QI_REG_P (operands[1]))"
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
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;; When source and destination does not overlap, clear destination
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;; first and then do the movb
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(define_split
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& QI_REG_P (operands[0])
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
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&& !reg_overlap_mentioned_p (operands[0], operands[1])"
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[(parallel [(set (match_dup 0) (const_int 0))
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(clobber (reg:CC 17))])
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(set (strict_low_part (subreg:QI (match_dup 0) 0)) (match_dup 1))]
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"")
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(define_split
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "memory_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& QI_REG_P (operands[0])
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& reg_overlap_mentioned_p (operands[0], operands[1])"
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[(set (strict_low_part (subreg:QI (match_dup 0) 0)) (match_dup 1))
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(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
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(clobber (reg:CC 17))])]
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"")
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[(set (match_dup 0) (const_int 0))
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(set (strict_low_part (match_dup 2)) (match_dup 1))]
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"operands[2] = gen_lowpart (QImode, operands[0]);")
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;; Rest is handled by single and.
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(define_split
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[(set (match_operand:HI 0 "register_operand" "")
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(zero_extend:HI (match_operand:QI 1 "register_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& ! reg_overlap_mentioned_p (operands[0], operands[1])"
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[(set (match_dup 0) (subreg:HI (match_dup 1) 0))
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(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
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&& true_regnum (operands[0]) == true_regnum (operands[1])"
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[(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
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(clobber (reg:CC 17))])]
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"")
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(define_insn "zero_extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "=q,r,r")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,0,qm")))
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(clobber (reg:CC 17))]
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(define_expand "zero_extendqisi2"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC 17))])]
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""
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_ALU1:
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if (!REG_P (operands[1]) || REGNO (operands[0]) != REGNO (operands[1]))
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abort ();
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operands[1] = GEN_INT (0xff);
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return \"and{l}\\t{%1, %0|%0, %1}\";
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default:
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return \"movz{bl|x}\\t{%1, %0|%0, %1}\";
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}
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}"
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[(set (attr "type")
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(cond [(and (eq_attr "alternative" "0")
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(ne (symbol_ref "TARGET_ZERO_EXTEND_WITH_AND")
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(const_int 0)))
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(const_string "alu1")
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(eq_attr "alternative" "1")
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(const_string "alu1")
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]
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(const_string "imovx")))])
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"")
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(define_insn "*zero_extendqisi2_and"
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[(set (match_operand:SI 0 "register_operand" "=r,?&q")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
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(clobber (reg:CC 17))]
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"TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
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"#"
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[(set_attr "type" "alu1")])
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(define_insn "*zero_extendqisi2_movzbw_and"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
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(clobber (reg:CC 17))]
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"!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
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"#"
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[(set_attr "type" "imovx,alu1")])
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(define_insn "*zero_extendqisi2_movzbw"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
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"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
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"movz{bl|x}\\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx")])
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;; For the movzbl case strip only the clobber
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& QI_REG_P (operands[0])
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&& (GET_CODE (operands[1]) == MEM || QI_REG_P (operands[1]))
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&& !reg_overlap_mentioned_p (operands[0], operands[1])"
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[(parallel [(set (match_dup 0) (const_int 0))
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(clobber (reg:CC 17))])
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(set (strict_low_part (subreg:QI (match_dup 0) 0)) (match_dup 1))]
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"")
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&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
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&& (!REG_P (operands[1]) || QI_REG_P (operands[1]))"
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[(set (match_dup 0)
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(zero_extend:SI (match_dup 1)))])
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;; When source and destination does not overlap, clear destination
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;; first and then do the movb
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& QI_REG_P (operands[0])
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&& (QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
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&& (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
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&& !reg_overlap_mentioned_p (operands[0], operands[1])"
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[(set (match_dup 0) (const_int 0))
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(set (strict_low_part (match_dup 2)) (match_dup 1))]
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"operands[2] = gen_lowpart (QImode, operands[0]);")
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;; Rest is handled by single and.
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:QI 1 "register_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& TARGET_ZERO_EXTEND_WITH_AND
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&& ! reg_overlap_mentioned_p (operands[0], operands[1])"
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[(set (match_dup 0) (subreg:SI (match_dup 1) 0))
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(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
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&& true_regnum (operands[0]) == true_regnum (operands[1])"
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[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
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(clobber (reg:CC 17))])]
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"")
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