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mips.c (symbol_operand): New function.
2002-06-19 Eric Christopher <echristo@redhat.com> * config/mips/mips.c (symbol_operand): New function. (mips_emit_prefetch): Ditto. * config/mips/mips-protos.h: Define. * config/mips/mips.h (ISA_HAS_PREFETCH): Define. (CONSTANT_ADDRESS_P): Adjust, use TARGET_GAS. (LEGITIMIZE_ADDRESS): Ditto. * config/mips/mips.md (prefetch, prefetch_si_address, prefetch_si, prefetch_di_address, prefetch_di): New patterns. From-SVN: r54805
This commit is contained in:
Eric Christopher
Eric Christopher
parent
ba3292dbb7
commit
8f2e3902df
@ -1,3 +1,14 @@
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2002-06-19 Eric Christopher <echristo@redhat.com>
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* config/mips/mips.c (symbol_operand): New function.
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(mips_emit_prefetch): Ditto.
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* config/mips/mips-protos.h: Define.
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* config/mips/mips.h (ISA_HAS_PREFETCH): Define.
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(CONSTANT_ADDRESS_P): Adjust, use TARGET_GAS.
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(LEGITIMIZE_ADDRESS): Ditto.
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* config/mips/mips.md (prefetch, prefetch_si_address,
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prefetch_si, prefetch_di_address, prefetch_di): New patterns.
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2002-06-19 Eric Christopher <echristo@redhat.com>
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* config/fp-bit.h: Add unordered defines for gofast.
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@ -98,6 +98,7 @@ extern const char *mips_fill_delay_slot PARAMS ((const char *,
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rtx));
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extern const char *mips_move_1word PARAMS ((rtx *, rtx, int));
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extern const char *mips_move_2words PARAMS ((rtx *, rtx));
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extern const char *mips_emit_prefetch PARAMS ((rtx *));
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extern const char *mips_restore_gp PARAMS ((rtx *, rtx));
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extern const char *output_block_move PARAMS ((rtx, rtx *, int,
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enum block_move_type));
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@ -90,6 +90,8 @@ int coprocessor_operand PARAMS ((rtx,
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enum machine_mode));
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int coprocessor2_operand PARAMS ((rtx,
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enum machine_mode));
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int symbolic_operand PARAMS ((rtx,
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enum machine_mode));
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static int m16_check_op PARAMS ((rtx, int, int, int));
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static void block_move_loop PARAMS ((rtx, rtx,
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unsigned int,
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@ -1384,6 +1386,26 @@ coprocessor2_operand (op, mode)
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&& REGNO (op) <= COP2_REG_LAST);
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}
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/* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
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possibly with an offset. */
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int
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symbolic_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
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return 0;
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if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
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return 1;
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if (GET_CODE (op) == CONST
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&& GET_CODE (XEXP (op,0)) == PLUS
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&& GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
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return 1;
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return 0;
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}
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/* Return nonzero if we split the address into high and low parts. */
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/* ??? We should also handle reg+array somewhere. We get four
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@ -10394,6 +10416,37 @@ mips_issue_rate ()
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return rate;
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}
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const char *
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mips_emit_prefetch (operands)
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rtx operands[];
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{
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/* For the mips32/64 architectures the hint fields are arranged
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by operation (load/store) and locality (normal/streamed/retained).
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Irritatingly, numbers 2 and 3 are reserved leaving no simple
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algorithm for figuring the hint. */
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int write = INTVAL (operands[1]);
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int locality = INTVAL (operands[2]);
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static const char * const alt[2][4] = {
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{
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"pref\t0,%a0",
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"pref\t4,%a0",
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"pref\t4,%a0",
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"pref\t6,%a0"
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},
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{
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"pref\t1,%a0",
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"pref\t5,%a0",
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"pref\t5,%a0",
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"pref\t7,%a0"
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}
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};
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return alt[write][locality];
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}
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#ifdef TARGET_IRIX6
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/* Output assembly to switch to section NAME with attribute FLAGS. */
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@ -685,7 +685,7 @@ extern void sbss_section PARAMS ((void));
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SUBTARGET_TARGET_OPTIONS \
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{ "cpu=", &mips_cpu_string, \
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N_("Specify CPU for scheduling purposes")}, \
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{ "tune=", &mips_tune_string, \
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{ "tune=", &mips_tune_string, \
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N_("Specify CPU for scheduling purposes")}, \
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{ "arch=", &mips_arch_string, \
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N_("Specify CPU for code generation purposes")}, \
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@ -725,14 +725,14 @@ extern void sbss_section PARAMS ((void));
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#define HAVE_SQRT_P() (!ISA_MIPS1)
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/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
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#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
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|| ISA_MIPS4 \
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#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
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|| ISA_MIPS4 \
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|| ISA_MIPS64)
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/* ISA has branch likely instructions (eg. mips2). */
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/* Disable branchlikely for tx39 until compare rewrite. They haven't
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been generated up to this point. */
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#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
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#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
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&& !TARGET_MIPS16)
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/* ISA has the conditional move instructions introduced in mips4. */
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@ -781,6 +781,12 @@ extern void sbss_section PARAMS ((void));
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#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
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&& !TARGET_MIPS16)
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/* ISA has data prefetch instruction. */
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#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
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|| ISA_MIPS32 \
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|| ISA_MIPS64) \
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&& !TARGET_MIPS16)
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/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
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-mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
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-mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
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@ -1060,7 +1066,7 @@ extern int mips_abi;
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%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
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%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
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%{mips32:-mfp32 -mgp32} \
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%{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
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%{mips64:%{!msingle-float:-mfp64} -mgp64} \
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%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
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%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
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%{mint64|mlong64|mlong32:-mexplicit-type-size }\
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@ -1343,21 +1349,21 @@ do { \
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#define PUT_SDB_FUNCTION_START(LINE)
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#define PUT_SDB_FUNCTION_END(LINE) \
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do { \
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extern FILE *asm_out_text_file; \
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#define PUT_SDB_FUNCTION_END(LINE) \
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do { \
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extern FILE *asm_out_text_file; \
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ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
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} while (0)
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#define PUT_SDB_EPILOGUE_END(NAME)
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#define PUT_SDB_SRC_FILE(FILENAME) \
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#define PUT_SDB_SRC_FILE(FILENAME) \
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do { \
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extern FILE *asm_out_text_file; \
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output_file_directive (asm_out_text_file, (FILENAME)); \
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output_file_directive (asm_out_text_file, (FILENAME));\
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} while (0)
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#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
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#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
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sprintf ((BUFFER), ".%dfake", (NUMBER));
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/* Correct the offset of automatic variables and arguments. Note that
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@ -1367,9 +1373,9 @@ do { \
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the frame pointer to be the stack pointer after the initial
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adjustment. */
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#define DEBUGGER_AUTO_OFFSET(X) \
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#define DEBUGGER_AUTO_OFFSET(X) \
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mips_debugger_offset (X, (HOST_WIDE_INT) 0)
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#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
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#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
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mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
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/* Tell collect that the object format is ECOFF */
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@ -2976,15 +2982,17 @@ typedef struct mips_args {
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assembler would use $at as a temp to load in the large offset. In this
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case $at is already in use. We convert such problem addresses to
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`la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
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/* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
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/* ??? SGI Irix 6 assembler fails for CONST address, so reject them
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when !TARGET_GAS. */
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/* We should be rejecting everything but const addresses. */
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#define CONSTANT_ADDRESS_P(X) \
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(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
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|| GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
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|| (GET_CODE (X) == CONST \
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&& ! (flag_pic && pic_address_needs_scratch (X)) \
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&& (mips_abi == ABI_32 \
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|| mips_abi == ABI_O64 \
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|| mips_abi == ABI_EABI)))
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&& (!TARGET_GAS) \
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&& (mips_abi == ABI_N32 \
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|| mips_abi == ABI_64)))
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/* Define this, so that when PIC, reload won't try to reload invalid
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addresses which require two reload registers. */
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@ -3075,9 +3083,9 @@ typedef struct mips_args {
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if (GET_CODE (xinsn) == CONST \
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&& ((flag_pic && pic_address_needs_scratch (xinsn)) \
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/* ??? SGI's Irix 6 assembler can't handle CONST. */ \
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|| (mips_abi != ABI_32 \
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&& mips_abi != ABI_O64 \
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&& mips_abi != ABI_EABI))) \
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|| (!TARGET_GAS \
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&& (mips_abi == ABI_N32 \
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|| mips_abi == ABI_64)))) \
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{ \
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rtx ptr_reg = gen_reg_rtx (Pmode); \
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rtx constant = XEXP (XEXP (xinsn, 0), 1); \
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@ -3447,11 +3455,11 @@ typedef struct mips_args {
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enum machine_mode xmode = GET_MODE (X); \
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if (xmode == SFmode) \
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{ \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900 \
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|| TUNE_MIPS5000) \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900 \
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|| TUNE_MIPS5000) \
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return COSTS_N_INSNS (4); \
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else if (TUNE_MIPS6000) \
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else if (TUNE_MIPS6000) \
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return COSTS_N_INSNS (5); \
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else \
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return COSTS_N_INSNS (7); \
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@ -3459,23 +3467,23 @@ typedef struct mips_args {
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\
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if (xmode == DFmode) \
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{ \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900 \
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|| TUNE_MIPS5000) \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900 \
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|| TUNE_MIPS5000) \
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return COSTS_N_INSNS (5); \
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else if (TUNE_MIPS6000) \
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else if (TUNE_MIPS6000) \
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return COSTS_N_INSNS (6); \
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else \
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return COSTS_N_INSNS (8); \
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} \
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\
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if (TUNE_MIPS3000) \
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if (TUNE_MIPS3000) \
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return COSTS_N_INSNS (12); \
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else if (TUNE_MIPS3900) \
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else if (TUNE_MIPS3900) \
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return COSTS_N_INSNS (2); \
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else if (TUNE_MIPS6000) \
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else if (TUNE_MIPS6000) \
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return COSTS_N_INSNS (17); \
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else if (TUNE_MIPS5000) \
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else if (TUNE_MIPS5000) \
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return COSTS_N_INSNS (5); \
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else \
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return COSTS_N_INSNS (10); \
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@ -3487,10 +3495,10 @@ typedef struct mips_args {
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enum machine_mode xmode = GET_MODE (X); \
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if (xmode == SFmode) \
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{ \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900) \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900) \
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return COSTS_N_INSNS (12); \
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else if (TUNE_MIPS6000) \
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else if (TUNE_MIPS6000) \
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return COSTS_N_INSNS (15); \
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else \
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return COSTS_N_INSNS (23); \
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@ -3498,10 +3506,10 @@ typedef struct mips_args {
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\
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if (xmode == DFmode) \
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{ \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900) \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900) \
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return COSTS_N_INSNS (19); \
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else if (TUNE_MIPS6000) \
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else if (TUNE_MIPS6000) \
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return COSTS_N_INSNS (16); \
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else \
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return COSTS_N_INSNS (36); \
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@ -3511,12 +3519,12 @@ typedef struct mips_args {
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\
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case UDIV: \
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case UMOD: \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900) \
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if (TUNE_MIPS3000 \
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|| TUNE_MIPS3900) \
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return COSTS_N_INSNS (35); \
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else if (TUNE_MIPS6000) \
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else if (TUNE_MIPS6000) \
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return COSTS_N_INSNS (38); \
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else if (TUNE_MIPS5000) \
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else if (TUNE_MIPS5000) \
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return COSTS_N_INSNS (36); \
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else \
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return COSTS_N_INSNS (69); \
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@ -10540,6 +10540,51 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
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;; ....................
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;;
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(define_expand "prefetch"
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[(prefetch (match_operand 0 "address_operand" "")
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(match_operand 1 "const_int_operand" "")
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(match_operand 2 "const_int_operand" ""))]
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"ISA_HAS_PREFETCH"
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"{
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if (symbolic_operand (operands[0], GET_MODE (operands[0])))
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operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
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}")
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(define_insn "prefetch_si_address"
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[(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 3 "const_int_operand" "i"))
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(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCH && Pmode == SImode"
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"* return mips_emit_prefetch (operands);"
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[(set_attr "type" "load")])
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(define_insn "prefetch_si"
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[(prefetch (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCH && Pmode == SImode"
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"* return mips_emit_prefetch (operands);"
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[(set_attr "type" "load")])
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(define_insn "prefetch_di_address"
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[(prefetch (plus:DI (match_operand:DI 0 "se_register_operand" "r")
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(match_operand:DI 3 "const_int_operand" "i"))
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(match_operand:DI 1 "const_int_operand" "n")
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(match_operand:DI 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCH && Pmode == DImode"
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"* return mips_emit_prefetch (operands);"
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[(set_attr "type" "load")])
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(define_insn "prefetch_di"
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[(prefetch (match_operand:DI 0 "se_register_operand" "r")
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(match_operand:DI 1 "const_int_operand" "n")
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(match_operand:DI 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCH && Pmode == DImode"
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"* return mips_emit_prefetch (operands);"
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[(set_attr "type" "load")])
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(define_insn "nop"
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[(const_int 0)]
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""
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