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arm: ACLE BFloat16 convert intrinsics
This patch is part of a series adding support for Armv8.6-A features. It implements intrinsics to convert between bfloat16 and float32 formats. gcc/ChangeLog: * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New. * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New. (vcvtq_high_f32_bf16, vcvt_bf16_f32): New. (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New. * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries. (vbfcvtv4sf, vbfcvtv4sf_high): Likewise. * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators. (V_bf_low, V_bf_cvt_m): New mode attributes. * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New. (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New. (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New. (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/bf16_cvt_1.c: New test.
This commit is contained in:
Dennis Zhang
parent
9b4f00dd3f
commit
8e6d0dba16
@ -1,3 +1,19 @@
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2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
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* config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
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* config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
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(vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
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(vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
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* config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
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(vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
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* config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
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(V_bf_low, V_bf_cvt_m): New mode attributes.
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* config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
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(neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
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(neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
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(neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
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* config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
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2020-03-03 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/93582
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@ -34,6 +34,20 @@ extern "C" {
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typedef __bf16 bfloat16_t;
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typedef float float32_t;
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__extension__ extern __inline float32_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvtah_f32_bf16 (bfloat16_t __a)
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{
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return __builtin_neon_vbfcvtbf (__a);
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}
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__extension__ extern __inline bfloat16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvth_bf16_f32 (float32_t __a)
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{
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return __builtin_neon_vbfcvtsf (__a);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -19379,6 +19379,55 @@ vbfdotq_lane_f32 (float32x4_t __r, bfloat16x8_t __a, bfloat16x4_t __b,
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#pragma GCC pop_options
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#pragma GCC push_options
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#pragma GCC target ("arch=armv8.2-a+bf16")
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvt_f32_bf16 (bfloat16x4_t __a)
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{
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return __builtin_neon_vbfcvtv4bf (__a);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvtq_low_f32_bf16 (bfloat16x8_t __a)
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{
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return __builtin_neon_vbfcvtv8bf (__a);
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}
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__extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvtq_high_f32_bf16 (bfloat16x8_t __a)
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{
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return __builtin_neon_vbfcvt_highv8bf (__a);
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}
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__extension__ extern __inline bfloat16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvt_bf16_f32 (float32x4_t __a)
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{
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return __builtin_neon_vbfcvtv4sfv4bf (__a);
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}
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__extension__ extern __inline bfloat16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvtq_low_bf16_f32 (float32x4_t __a)
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{
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return __builtin_neon_vbfcvtv4sfv8bf (__a);
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}
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/* The 'inactive' operand is not converted but it provides the
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low 64 bits to assemble the final 128-bit result. */
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__extension__ extern __inline bfloat16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vcvtq_high_bf16_f32 (bfloat16x8_t inactive, float32x4_t __a)
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{
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return __builtin_neon_vbfcvtv4sf_highv8bf (inactive, __a);
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}
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#pragma GCC pop_options
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#ifdef __cplusplus
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}
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#endif
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@ -385,3 +385,9 @@ VAR1 (USTERNOP, usmmla, v16qi)
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VAR2 (TERNOP, vbfdot, v2sf, v4sf)
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VAR2 (MAC_LANE_PAIR, vbfdot_lanev4bf, v2sf, v4sf)
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VAR2 (MAC_LANE_PAIR, vbfdot_lanev8bf, v2sf, v4sf)
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VAR2 (UNOP, vbfcvt, sf, bf)
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VAR2 (UNOP, vbfcvt, v4bf, v8bf)
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VAR1 (UNOP, vbfcvt_high, v8bf)
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VAR2 (UNOP, vbfcvtv4sf, v4bf, v8bf)
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VAR1 (BINOP, vbfcvtv4sf_high, v8bf)
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@ -229,6 +229,10 @@
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;; Modes for polynomial or float values.
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(define_mode_iterator VPF [V8QI V16QI V2SF V4SF])
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;; Modes for BF16 convert instructions.
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(define_mode_iterator VBFCVT [V4BF V8BF])
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(define_mode_iterator VBFCVTM [V2SI SF])
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;;----------------------------------------------------------------------------
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;; Code iterators
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;;----------------------------------------------------------------------------
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@ -747,6 +751,12 @@
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(V2SF "") (V4SF "")
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(DI "_neon") (V2DI "")])
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;; To select the low 64 bits of a vector.
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(define_mode_attr V_bf_low [(V4BF "P") (V8BF "e")])
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;; To generate intermediate modes for BF16 scalar convert.
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(define_mode_attr V_bf_cvt_m [(V2SI "BF") (SF "V2SI")])
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;; Scalars to be presented to scalar multiplication instructions
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;; must satisfy the following constraints.
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@ -6660,3 +6660,80 @@ if (BYTES_BIG_ENDIAN)
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}
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[(set_attr "type" "neon_dot<q>")]
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)
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(define_insn "neon_vbfcvtv4sf<VBFCVT:mode>"
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[(set (match_operand:VBFCVT 0 "register_operand" "=w")
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(unspec:VBFCVT [(match_operand:V4SF 1 "register_operand" "w")]
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UNSPEC_BFCVT))]
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"TARGET_BF16_SIMD"
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"vcvt.bf16.f32\\t%<V_bf_low>0, %q1"
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[(set_attr "type" "neon_fp_cvt_narrow_s_q")]
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)
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(define_insn "neon_vbfcvtv4sf_highv8bf"
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[(set (match_operand:V8BF 0 "register_operand" "=w")
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(unspec:V8BF [(match_operand:V8BF 1 "register_operand" "0")
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(match_operand:V4SF 2 "register_operand" "w")]
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UNSPEC_BFCVT_HIGH))]
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"TARGET_BF16_SIMD"
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"vcvt.bf16.f32\\t%f0, %q2"
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[(set_attr "type" "neon_fp_cvt_narrow_s_q")]
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)
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(define_insn "neon_vbfcvtsf"
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[(set (match_operand:BF 0 "register_operand" "=t")
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(unspec:BF [(match_operand:SF 1 "register_operand" "t")]
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UNSPEC_BFCVT))]
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"TARGET_BF16_FP"
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"vcvtb.bf16.f32\\t%0, %1"
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[(set_attr "type" "f_cvt")]
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)
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(define_insn "neon_vbfcvt<VBFCVT:mode>"
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[(set (match_operand:V4SF 0 "register_operand" "=w")
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(unspec:V4SF [(match_operand:VBFCVT 1 "register_operand" "w")]
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UNSPEC_BFCVT))]
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"TARGET_BF16_SIMD"
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"vshll.u32\\t%q0, %<V_bf_low>1, #16"
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[(set_attr "type" "neon_shift_imm_q")]
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)
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(define_insn "neon_vbfcvt_highv8bf"
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[(set (match_operand:V4SF 0 "register_operand" "=w")
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(unspec:V4SF [(match_operand:V8BF 1 "register_operand" "w")]
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UNSPEC_BFCVT_HIGH))]
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"TARGET_BF16_SIMD"
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"vshll.u32\\t%q0, %f1, #16"
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[(set_attr "type" "neon_shift_imm_q")]
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)
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;; Convert a BF scalar operand to SF via VSHL.
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;; VSHL doesn't accept 32-bit registers where the BF and SF scalar operands
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;; would be allocated, therefore the operands must be converted to intermediate
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;; vectors (i.e. V2SI) in order to apply 64-bit registers.
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(define_expand "neon_vbfcvtbf"
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[(match_operand:SF 0 "register_operand")
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(unspec:SF [(match_operand:BF 1 "register_operand")] UNSPEC_BFCVT)]
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"TARGET_BF16_FP"
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{
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rtx op0 = gen_reg_rtx (V2SImode);
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rtx op1 = gen_reg_rtx (V2SImode);
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emit_insn (gen_neon_vbfcvtbf_cvtmodev2si (op1, operands[1]));
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emit_insn (gen_neon_vshl_nv2si (op0, op1, gen_int_mode(16, SImode)));
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emit_insn (gen_neon_vbfcvtbf_cvtmodesf (operands[0], op0));
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DONE;
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})
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;; Convert BF mode to V2SI and V2SI to SF.
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;; Implement this by allocating a 32-bit operand in the low half of a 64-bit
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;; register indexed by a 32-bit sub-register number.
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;; This will generate reloads but compiler can optimize out the moves.
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;; Use 'x' constraint to guarantee the 32-bit sub-registers in an indexable
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;; range so that to avoid extra moves.
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(define_insn "neon_vbfcvtbf_cvtmode<mode>"
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[(set (match_operand:VBFCVTM 0 "register_operand" "=x")
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(unspec:VBFCVTM [(match_operand:<V_bf_cvt_m> 1 "register_operand" "0")]
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UNSPEC_BFCVT))]
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"TARGET_BF16_FP"
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""
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)
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@ -506,4 +506,6 @@
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UNSPEC_MATMUL_S
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UNSPEC_MATMUL_U
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UNSPEC_MATMUL_US
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UNSPEC_BFCVT
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UNSPEC_BFCVT_HIGH
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])
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@ -1,3 +1,7 @@
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2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
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* gcc.target/arm/simd/bf16_cvt_1.c: New test.
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2020-03-03 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/93582
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51
gcc/testsuite/gcc.target/arm/simd/bf16_cvt_1.c
Normal file
51
gcc/testsuite/gcc.target/arm/simd/bf16_cvt_1.c
Normal file
@ -0,0 +1,51 @@
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/* { dg-do assemble } */
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/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
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/* { dg-options "-save-temps -O2" } */
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/* { dg-add-options arm_v8_2a_bf16_neon } */
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#include "arm_neon.h"
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float32_t test_vcvtah_f32_bf16 (bfloat16_t a)
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{
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return vcvtah_f32_bf16 (a);
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}
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bfloat16_t test_vcvth_bf16_f32 (float32_t a)
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{
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return vcvth_bf16_f32 (a);
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}
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float32x4_t test_vcvt_f32_bf16 (bfloat16x4_t a)
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{
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return vcvt_f32_bf16 (a);
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}
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float32x4_t test_vcvtq_low_f32_bf16 (bfloat16x8_t a)
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{
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return vcvtq_low_f32_bf16 (a);
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}
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float32x4_t test_vcvtq_high_f32_bf16 (bfloat16x8_t a)
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{
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return vcvtq_high_f32_bf16 (a);
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}
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bfloat16x4_t test_vcvt_bf16_f32 (float32x4_t a)
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{
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return vcvt_bf16_f32 (a);
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}
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bfloat16x8_t test_vcvtq_low_bf16_f32 (float32x4_t a)
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{
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return vcvtq_low_bf16_f32 (a);
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}
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bfloat16x8_t test_vcvtq_high_bf16_f32 (bfloat16x8_t inactive, float32x4_t a)
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{
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return vcvtq_high_bf16_f32 (inactive, a);
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}
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/* { dg-final { scan-assembler-times {vcvtb.bf16.f32\ts[0-9]+, s[0-9]+\n} 1 } } */
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/* { dg-final { scan-assembler-times {vcvt.bf16.f32\td[0-9]+, q[0-9]+\n} 3 } } */
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/* { dg-final { scan-assembler-times {vshl.i32\td[0-9]+, d[0-9]+, #16} 1 } } */
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/* { dg-final { scan-assembler-times {vshll.u32\tq[0-9]+, d[0-9]+, #16} 3 } } */
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