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[ARC] Update mlo/mhi handling when big-endian CPU.

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gcc/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
	registers.
	(umulsidi_600): Likewise.

testsuite/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>
	Petro Karashchenko  <petro.karashchenko@ring.com>

	* estsuite/gcc.target/arc/mul64-1.c: New test.
This commit is contained in:
Claudiu Zissulescu 2020-02-13 12:32:05 +02:00
parent ae2b8ede40
commit 8dca38c43c
4 changed files with 66 additions and 18 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi
registers.
(umulsidi_600): Likewise.
2020-02-13 Jakub Jelinek <jakub@redhat.com>
PR target/93696

50
gcc/config/arc/arc.md
View File

@ -2275,19 +2275,26 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(set_attr "cond" "canuse,canuse,canuse_limm,canuse")])
(define_insn_and_split "mulsidi_600"
[(set (match_operand:DI 0 "register_operand" "=c, c,c, c")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%Rcq#q, c,c, c"))
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "Rcq#q,cL,L,C32"))))
(clobber (reg:DI MUL64_OUT_REG))]
[(set (match_operand:DI 0 "register_operand" "=r,r, r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r,r, r"))
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "rL,L,C32"))))
(clobber (reg:DI R58_REG))]
"TARGET_MUL64_SET"
"#"
"TARGET_MUL64_SET"
"TARGET_MUL64_SET && reload_completed"
[(const_int 0)]
"emit_insn (gen_mul64 (operands[1], operands[2]));
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
DONE;"
{
int hi = !TARGET_BIG_ENDIAN;
int lo = !hi;
rtx lr = operand_subword (operands[0], lo, 0, DImode);
rtx hr = operand_subword (operands[0], hi, 0, DImode);
emit_insn (gen_mul64 (operands[1], operands[2]));
emit_move_insn (lr, gen_rtx_REG (SImode, R58_REG));
emit_move_insn (hr, gen_rtx_REG (SImode, R59_REG));
DONE;
}
[(set_attr "type" "multi")
(set_attr "length" "8")])
(set_attr "length" "4,4,8")])
(define_insn "mul64"
[(set (reg:DI MUL64_OUT_REG)
@ -2303,19 +2310,26 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(set_attr "cond" "canuse,canuse,canuse_limm,canuse")])
(define_insn_and_split "umulsidi_600"
[(set (match_operand:DI 0 "register_operand" "=c,c, c")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c,c, c"))
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "cL,L,C32"))))
(clobber (reg:DI MUL64_OUT_REG))]
[(set (match_operand:DI 0 "register_operand" "=r,r, r")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r,r, r"))
(zero_extend:DI (match_operand:SI 2 "nonmemory_operand" "rL,L,C32"))))
(clobber (reg:DI R58_REG))]
"TARGET_MUL64_SET"
"#"
"TARGET_MUL64_SET"
"TARGET_MUL64_SET && reload_completed"
[(const_int 0)]
"emit_insn (gen_mulu64 (operands[1], operands[2]));
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
DONE;"
{
int hi = !TARGET_BIG_ENDIAN;
int lo = !hi;
rtx lr = operand_subword (operands[0], lo, 0, DImode);
rtx hr = operand_subword (operands[0], hi, 0, DImode);
emit_insn (gen_mulu64 (operands[1], operands[2]));
emit_move_insn (lr, gen_rtx_REG (SImode, R58_REG));
emit_move_insn (hr, gen_rtx_REG (SImode, R59_REG));
DONE;
}
[(set_attr "type" "umulti")
(set_attr "length" "8")])
(set_attr "length" "4,4,8")])
(define_insn "mulu64"
[(set (reg:DI MUL64_OUT_REG)

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
Petro Karashchenko <petro.karashchenko@ring.com>
* gcc.target/arc/mul64-1.c: New test.
2020-02-13 Jakub Jelinek <jakub@redhat.com>
PR target/93696

23
gcc/testsuite/gcc.target/arc/mul64-1.c Normal file
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@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-skip-if "MUL64 is ARC600 extension." { ! { clmcpu } } } */
/* { dg-options "-O2 -mmul64 -mbig-endian -mcpu=arc600" } */
/* Check if mlo/mhi registers are correctly layout when we compile for
a big-endian CPU. */
#include <stdint.h>
uint32_t foo (uint32_t x)
{
return x % 1000;
}
int32_t bar (int32_t x)
{
return x % 1000;
}
/* { dg-final { scan-assembler-times "\\s+mul64\\s+" 3 } } */
/* { dg-final { scan-assembler-times "\\s+mulu64\\s+" 1 } } */
/* { dg-final { scan-assembler-times "r\[0-9\]+,mhi" 2 } } */
/* { dg-final { scan-assembler-times "r\[0-9\]+,mlo" 2 } } */