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rs6000: wf -> wa

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"wf" is just "wa".


	* config/rs6000/constraints.md (define_register_constraint "wf"):
	Delete.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wf.
	* config/rs6000/rs6000.md: Adjust.
	* config/rs6000/vsx.md: Adjust.
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271921
This commit is contained in:
Segher Boessenkool 2019-06-04 18:51:53 +02:00 committed by Segher Boessenkool
parent 10078f3e1d
commit 8d3620baab
7 changed files with 50 additions and 55 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/constraints.md (define_register_constraint "wf"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_wf.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
2019-06-04 Andrew Pinski <apinski@marvell.com>
* config/aarch64/aarch64.c (aarch64_asan_shadow_offset):

3
gcc/config/rs6000/constraints.md
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@ -62,9 +62,6 @@
(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]"
"VSX register if the -mpower9-vector -m64 options were used or NO_REGS.")
(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]"
"VSX vector register to hold vector float data or NO_REGS.")
;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use
;; direct move directly, and movsf can't to move between the register sets.
;; There is a mode_attr that resolves to wa for SDmode and wn for SFmode

8
gcc/config/rs6000/rs6000.c
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@ -2509,7 +2509,6 @@ rs6000_debug_reg_global (void)
"v reg_class = %s\n"
"wa reg_class = %s\n"
"we reg_class = %s\n"
"wf reg_class = %s\n"
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
@ -2522,7 +2521,6 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
@ -3136,7 +3134,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
v - Altivec register.
wa - Any VSX register.
wc - Reserved to represent individual CR bits (used in LLVM).
wf - Preferred register class for V4SFmode.
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ww - Register class to do SF conversions in with VSX operations.
@ -3149,10 +3146,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
}
if (TARGET_VSX)
{
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
}
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
/* Add conditional constraints based on various options, to allow us to
collapse multiple insn patterns. */

1
gcc/config/rs6000/rs6000.h
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@ -1257,7 +1257,6 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_v, /* Altivec registers */
RS6000_CONSTRAINT_wa, /* Any VSX register */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */

2
gcc/config/rs6000/rs6000.md
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@ -624,7 +624,7 @@
(DF "wa")
(TF "f")
(TD "f")
(V4SF "wf")
(V4SF "wa")
(V2DF "wa")])
(define_mode_attr rreg2 [(SF "f")

74
gcc/config/rs6000/vsx.md
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@ -111,7 +111,7 @@
(define_mode_attr VSr [(V16QI "v")
(V8HI "v")
(V4SI "v")
(V4SF "wf")
(V4SF "wa")
(V2DI "wa")
(V2DF "wa")
(DI "wa")
@ -126,7 +126,7 @@
;; VSr2 is the preferred register class, VSr3 is any register class that will
;; hold the data
(define_mode_attr VSr2 [(V2DF "wa")
(V4SF "wf")
(V4SF "wa")
(DF "wa")
(SF "ww")
(DI "wa")
@ -1904,15 +1904,13 @@
;; multiply.
(define_insn "*vsx_fmav4sf4"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(fma:V4SF
(match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v")
(match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v")
(match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))]
(match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
(match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
xvmaddasp %x0,%x1,%x2
xvmaddmsp %x0,%x1,%x3
vmaddfp %0,%1,%2,%3"
@ -1961,17 +1959,15 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,v")
(neg:V4SF
(fma:V4SF
(match_operand:V4SF 1 "vsx_register_operand" "%wf,wf,wa,wa,v")
(match_operand:V4SF 2 "vsx_register_operand" "wf,0,wa,0,v")
(match_operand:V4SF 1 "vsx_register_operand" "%wa,wa,v")
(match_operand:V4SF 2 "vsx_register_operand" "wa,0,v")
(neg:V4SF
(match_operand:V4SF 3 "vsx_register_operand" "0,wf,0,wa,v")))))]
(match_operand:V4SF 3 "vsx_register_operand" "0,wa,v")))))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"@
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
xvnmsubasp %x0,%x1,%x2
xvnmsubmsp %x0,%x1,%x3
vnmsubfp %0,%1,%2,%3"
@ -2410,24 +2406,24 @@
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvsxdsp"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvsxdsp %x0,%x1"
[(set_attr "type" "vecfloat")])
(define_insn "vsx_xvcvuxdsp"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVUXDSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvuxdsp %x0,%x1"
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcdpsp"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_XVCDPSP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvdpsp %x0,%x1"
@ -2436,8 +2432,8 @@
;; Convert from 32-bit to 64-bit types
;; Provide both vector and scalar targets
(define_insn "vsx_xvcvsxwdp"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvsxwdp %x0,%x1"
@ -2452,8 +2448,8 @@
[(set_attr "type" "vecdouble")])
(define_insn "vsx_xvcvuxwdp"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa,?wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wf,wa")]
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVUXWDP))]
"VECTOR_UNIT_VSX_P (V2DFmode)"
"xvcvuxwdp %x0,%x1"
@ -4225,11 +4221,11 @@
;; V4SF/V4SI interleave
(define_insn "vsx_xxmrghw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(match_operand:VSX_W 2 "vsx_register_operand" "wf,<VSa>"))
(match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>")
(match_operand:VSX_W 2 "vsx_register_operand" "wa,<VSa>"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -4242,11 +4238,11 @@
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxmrglw_<mode>"
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
[(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(match_operand:VSX_W 2 "vsx_register_operand" "wf,?<VSa>"))
(match_operand:VSX_W 1 "vsx_register_operand" "wa,<VSa>")
(match_operand:VSX_W 2 "vsx_register_operand" "wa,?<VSa>"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@ -4300,12 +4296,12 @@
(set_attr "type" "veccomplex")])
(define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
[(set (match_operand:V4SF 0 "vfloat_operand" "=wf,?wa")
[(set (match_operand:V4SF 0 "vfloat_operand" "=wa")
(VEC_reduc:V4SF
(unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
(match_operand:V4SF 1 "vfloat_operand" "wf,wa")))
(clobber (match_scratch:V4SF 2 "=&wf,&wa"))
(clobber (match_scratch:V4SF 3 "=&wf,&wa"))]
(match_operand:V4SF 1 "vfloat_operand" "wa")))
(clobber (match_scratch:V4SF 2 "=&wa"))
(clobber (match_scratch:V4SF 3 "=&wa"))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"#"
""
@ -4372,15 +4368,15 @@
(set_attr "type" "veccomplex")])
(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v4sf_scalar"
[(set (match_operand:SF 0 "vfloat_operand" "=f,?f")
[(set (match_operand:SF 0 "vfloat_operand" "=f")
(vec_select:SF
(VEC_reduc:V4SF
(unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
(match_operand:V4SF 1 "vfloat_operand" "wf,wa"))
(match_operand:V4SF 1 "vfloat_operand" "wa"))
(parallel [(const_int 3)])))
(clobber (match_scratch:V4SF 2 "=&wf,&wa"))
(clobber (match_scratch:V4SF 3 "=&wf,&wa"))
(clobber (match_scratch:V4SF 4 "=0,0"))]
(clobber (match_scratch:V4SF 2 "=&wa"))
(clobber (match_scratch:V4SF 3 "=&wa"))
(clobber (match_scratch:V4SF 4 "=0"))]
"BYTES_BIG_ENDIAN && VECTOR_UNIT_VSX_P (V4SFmode)"
"#"
""

5
gcc/doc/md.texi
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@ -3196,7 +3196,7 @@ Altivec vector register
@item wa
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa}, @code{wf},
When using any of the register constraints (@code{wa},
@code{wp}, @code{wq}, or @code{ww})
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
@ -3248,9 +3248,6 @@ is incorrect.
VSX register if the @option{-mcpu=power9} and @option{-m64} options
were used or NO_REGS.
@item wf
VSX vector register to hold vector float data or NO_REGS.
@item wn
No register (NO_REGS).