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* pa.md (reload shift-add patterns): Remove.

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From-SVN: r30688
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Jeffrey A Law 1999-11-28 20:24:48 +00:00 committed by Jeff Law
parent 2e02044af4
commit 8b4b9b7ad3
2 changed files with 4 additions and 41 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
Sun Nov 28 13:21:00 1999 Jeffrey A Law (law@cygnus.com)
* pa.md (reload shift-add patterns): Remove.
1999-11-28 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl>
* reorg.c (dbr_schedule) Print more statistics. Corrected

41
gcc/config/pa/pa.md
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@ -3118,25 +3118,6 @@
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4")])
;; Disgusting kludge to work around reload bugs with frame pointer
;; elimination. Similar to other magic reload patterns in the
;; indexed memory operations.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
(plus:SI (plus:SI (match_operand:SI 1 "register_operand" "%r")
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "const_int_operand" "rL")))]
"reload_in_progress"
"*
{
if (GET_CODE (operands[3]) == CONST_INT)
return \"ldo %3(%2),%0\;{addl|add,l} %1,%0,%0\";
else
return \"{addl|add,l} %3,%2,%0\;{addl|add,l} %1,%0,%0\";
}"
[(set_attr "type" "binary")
(set_attr "length" "8")])
(define_expand "subdi3"
[(set (match_operand:DI 0 "register_operand" "")
(minus:DI (match_operand:DI 1 "register_operand" "")
@ -4223,28 +4204,6 @@
[(set_attr "type" "binary")
(set_attr "length" "4")])
;; This variant of the above insn can occur if the first operand
;; is the frame pointer. This is a kludge, but there doesn't
;; seem to be a way around it. Only recognize it while reloading.
;; Note how operand 3 uses a predicate of "const_int_operand", but
;; has constraints allowing a register. I don't know how this works,
;; but it somehow makes sure that out-of-range constants are placed
;; in a register which somehow magically is a "const_int_operand".
;; (this was stolen from alpha.md, I'm not going to try and change it.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r,r")
(plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r")
(match_operand:SI 4 "shadd_operand" ""))
(match_operand:SI 1 "register_operand" "r,r"))
(match_operand:SI 3 "const_int_operand" "r,J")))]
"reload_in_progress"
"@
{sh%O4addl %2,%1,%0|shladd,l %2,%O4,%1,%0}\;{addl|add,l} %3,%0,%0
{sh%O4addl %2,%1,%0|shladd,l %2,%O4,%1,%0}\;ldo %3(%0),%0"
[(set_attr "type" "multi")
(set_attr "length" "8")])
;; This anonymous pattern and splitter wins because it reduces the latency
;; of the shadd sequence without increasing the latency of the shift.
;;