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i386.md (UNSPEC_BSF): Remove.
* config/i386/i386.md (UNSPEC_BSF): Remove.
(ffssi2): Split into cmove and no_cmove insns and splitters;
lose pentium float trick for now.
(ffssi_1): Add * to name; use CTZ instead of UNSPEC.
(ctzsi2, clzsi2, bsr): New.
From-SVN: r62434
This commit is contained in:
Richard Henderson
Richard Henderson
parent
c407570a72
commit
8acfdd43da
@ -1,3 +1,11 @@
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2003-02-04 Richard Henderson <rth@redhat.com>
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* config/i386/i386.md (UNSPEC_BSF): Remove.
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(ffssi2): Split into cmove and no_cmove insns and splitters;
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lose pentium float trick for now.
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(ffssi_1): Add * to name; use CTZ instead of UNSPEC.
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(ctzsi2, clzsi2, bsr): New.
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2003-02-04 Richard Henderson <rth@redhat.com>
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* config/ia64/ia64.c (rtx_needs_barrier): Handle POPCOUNT,
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@ -80,7 +80,6 @@
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(UNSPEC_SCAS 20)
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(UNSPEC_SIN 21)
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(UNSPEC_COS 22)
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(UNSPEC_BSF 23)
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(UNSPEC_FNSTSW 24)
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(UNSPEC_SAHF 25)
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(UNSPEC_FSTCW 26)
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@ -14110,104 +14109,98 @@
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[(set_attr "type" "leave")])
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(define_expand "ffssi2"
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "")
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(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
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(clobber (match_scratch:SI 2 ""))
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(clobber (reg:CC 17))])]
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""
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"")
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(define_insn_and_split "*ffs_cmove"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
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(clobber (match_scratch:SI 2 "=&r"))
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(clobber (reg:CC 17))]
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"TARGET_CMOVE"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (const_int -1))
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(parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
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(set (match_dup 0) (ctz:SI (match_dup 1)))])
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(set (match_dup 0) (if_then_else:SI
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(eq (reg:CCZ 17) (const_int 0))
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(match_dup 2)
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(match_dup 0)))
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(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
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(clobber (reg:CC 17))])]
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"")
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(define_insn_and_split "*ffs_no_cmove"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r")
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(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
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(clobber (match_scratch:SI 2 "=&r"))
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(clobber (reg:CC 17))]
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""
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"#"
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"reload_completed"
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[(parallel [(set (match_dup 2) (const_int 0))
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(clobber (reg:CC 17))])
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(parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
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(set (match_dup 0) (ctz:SI (match_dup 1)))])
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(set (strict_low_part (match_dup 3))
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(eq:QI (reg:CCZ 17) (const_int 0)))
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(parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
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(clobber (reg:CC 17))])
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(parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
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(clobber (reg:CC 17))])
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(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
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(clobber (reg:CC 17))])]
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{
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rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
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rtx in = operands[1];
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if (TARGET_CMOVE)
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{
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emit_move_insn (tmp, constm1_rtx);
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emit_insn (gen_ffssi_1 (out, in));
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emit_insn (gen_rtx_SET (VOIDmode, out,
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gen_rtx_IF_THEN_ELSE (SImode,
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gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
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const0_rtx),
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tmp,
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out)));
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emit_insn (gen_addsi3 (out, out, const1_rtx));
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emit_move_insn (operands[0], out);
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}
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/* Pentium bsf instruction is extremely slow. The following code is
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recommended by the Intel Optimizing Manual as a reasonable replacement:
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TEST EAX,EAX
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JZ SHORT BS2
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XOR ECX,ECX
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MOV DWORD PTR [TEMP+4],ECX
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SUB ECX,EAX
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AND EAX,ECX
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MOV DWORD PTR [TEMP],EAX
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FILD QWORD PTR [TEMP]
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FSTP QWORD PTR [TEMP]
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WAIT ; WAIT only needed for compatibility with
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; earlier processors
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MOV ECX, DWORD PTR [TEMP+4]
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SHR ECX,20
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SUB ECX,3FFH
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TEST EAX,EAX ; clear zero flag
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BS2:
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Following piece of code expand ffs to similar beast.
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*/
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else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
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{
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rtx label = gen_label_rtx ();
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rtx lo, hi;
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rtx mem = assign_386_stack_local (DImode, 0);
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rtx fptmp = gen_reg_rtx (DFmode);
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split_di (&mem, 1, &lo, &hi);
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emit_move_insn (out, const0_rtx);
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emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label);
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emit_move_insn (hi, out);
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emit_insn (gen_subsi3 (out, out, in));
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emit_insn (gen_andsi3 (out, out, in));
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emit_move_insn (lo, out);
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emit_insn (gen_floatdidf2 (fptmp,mem));
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emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
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emit_move_insn (out, hi);
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emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
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emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
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emit_label (label);
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LABEL_NUSES (label) = 1;
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emit_move_insn (operands[0], out);
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}
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else
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{
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emit_move_insn (tmp, const0_rtx);
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emit_insn (gen_ffssi_1 (out, in));
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emit_insn (gen_rtx_SET (VOIDmode,
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gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
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gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
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const0_rtx)));
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emit_insn (gen_negsi2 (tmp, tmp));
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emit_insn (gen_iorsi3 (out, out, tmp));
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emit_insn (gen_addsi3 (out, out, const1_rtx));
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emit_move_insn (operands[0], out);
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}
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DONE;
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operands[3] = gen_lowpart (QImode, operands[2]);
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})
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(define_insn "ffssi_1"
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(define_insn "*ffssi_1"
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[(set (reg:CCZ 17)
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(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
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(compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_dup 1)] UNSPEC_BSF))]
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(ctz:SI (match_dup 1)))]
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""
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"bsf{l}\t{%1, %0|%0, %1}"
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[(set_attr "prefix_0f" "1")
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(set_attr "ppro_uops" "few")])
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;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
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;; and slower than the two-byte movzx insn needed to do the work in SImode.
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(define_insn "ctzsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
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(clobber (reg:CC 17))]
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""
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"bsf{l}\t{%1, %0|%0, %1}"
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[(set_attr "prefix_0f" "1")
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(set_attr "ppro_uops" "few")])
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(define_expand "clzsi2"
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[(parallel
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[(set (match_operand:SI 0 "register_operand" "")
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(minus:SI (const_int 31)
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(clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
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(clobber (reg:CC 17))])
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(parallel
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[(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
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(clobber (reg:CC 17))])]
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""
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"")
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(define_insn "*bsr"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (const_int 31)
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(clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
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(clobber (reg:CC 17))]
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""
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"bsr{l}\t{%1, %0|%0, %1}"
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[(set_attr "prefix_0f" "1")
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(set_attr "ppro_uops" "few")])
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;; Thread-local storage patterns for ELF.
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;;
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