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[PR target/97726] arm: [testsuite] fix some simd tests on armbe
2020-11-10 Andrea Corallo <andrea.corallo@arm.com> PR target/97726 * gcc.target/arm/simd/bf16_vldn_1.c: Relax regexps not to fail on big endian. * gcc.target/arm/simd/vldn_lane_bf16_1.c: Likewise * gcc.target/arm/simd/vmmla_1.c: Add -mfloat-abi=hard flag.
This commit is contained in:
Andrea Corallo
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ad318e3f1d
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@ -10,8 +10,8 @@
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/*
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**test_vld2_bf16:
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** ...
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** vld2.16 {d0-d1}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x2_t
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test_vld2_bf16 (bfloat16_t * ptr)
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@ -22,8 +22,8 @@ test_vld2_bf16 (bfloat16_t * ptr)
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/*
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**test_vld2q_bf16:
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** ...
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** vld2.16 {d0-d3}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x2_t
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test_vld2q_bf16 (bfloat16_t * ptr)
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@ -34,8 +34,8 @@ test_vld2q_bf16 (bfloat16_t * ptr)
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/*
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**test_vld2_dup_bf16:
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** ...
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** vld2.16 {d0\[\], d1\[\]}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x2_t
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test_vld2_dup_bf16 (bfloat16_t * ptr)
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@ -46,8 +46,8 @@ test_vld2_dup_bf16 (bfloat16_t * ptr)
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/*
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**test_vld2q_dup_bf16:
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** ...
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** vld2.16 {d0, d1, d2, d3}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x2_t
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test_vld2q_dup_bf16 (bfloat16_t * ptr)
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@ -58,8 +58,8 @@ test_vld2q_dup_bf16 (bfloat16_t * ptr)
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/*
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**test_vld3_bf16:
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** ...
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** vld3.16 {d0-d2}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x3_t
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test_vld3_bf16 (bfloat16_t * ptr)
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@ -70,8 +70,8 @@ test_vld3_bf16 (bfloat16_t * ptr)
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/*
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**test_vld3q_bf16:
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** ...
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** vld3.16 {d1, d3, d5}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+, d[0-9]+, d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x3_t
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test_vld3q_bf16 (bfloat16_t * ptr)
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@ -82,8 +82,8 @@ test_vld3q_bf16 (bfloat16_t * ptr)
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/*
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**test_vld3_dup_bf16:
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** ...
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** vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x3_t
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test_vld3_dup_bf16 (bfloat16_t * ptr)
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@ -94,8 +94,8 @@ test_vld3_dup_bf16 (bfloat16_t * ptr)
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/*
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**test_vld3q_dup_bf16:
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** ...
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** vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\]
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** bx lr
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** vld[0-9]+.16 {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x3_t
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test_vld3q_dup_bf16 (bfloat16_t * ptr)
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@ -106,8 +106,8 @@ test_vld3q_dup_bf16 (bfloat16_t * ptr)
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/*
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**test_vld4_bf16:
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** ...
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** vld4.16 {d0-d3}, \[r0\]
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** bx lr
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** vld4.16 {d[0-9]+-d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x4_t
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test_vld4_bf16 (bfloat16_t * ptr)
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@ -118,8 +118,8 @@ test_vld4_bf16 (bfloat16_t * ptr)
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/*
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**test_vld4q_bf16:
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** ...
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** vld4.16 {d1, d3, d5, d7}, \[r0\]
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** bx lr
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** vld4.16 {d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x4_t
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test_vld4q_bf16 (bfloat16_t * ptr)
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@ -130,8 +130,8 @@ test_vld4q_bf16 (bfloat16_t * ptr)
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/*
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**test_vld4_dup_bf16:
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** ...
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** vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\]
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** bx lr
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** vld4.16 {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x4_t
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test_vld4_dup_bf16 (bfloat16_t * ptr)
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@ -142,8 +142,8 @@ test_vld4_dup_bf16 (bfloat16_t * ptr)
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/*
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**test_vld4q_dup_bf16:
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** ...
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** vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\]
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** bx lr
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** vld4.16 {d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\], d[0-9]+\[\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x4_t
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test_vld4q_dup_bf16 (bfloat16_t * ptr)
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@ -8,8 +8,9 @@
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/*
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**test_vld2_lane_bf16:
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** vld2.16 {d0\[2\], d1\[2\]}, \[r0\]
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** bx lr
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** ...
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** vld2.16 {d[0-9]+\[2\], d[0-9]+\[2\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x2_t
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test_vld2_lane_bf16 (const bfloat16_t *a, bfloat16x4x2_t b)
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@ -19,8 +20,9 @@ test_vld2_lane_bf16 (const bfloat16_t *a, bfloat16x4x2_t b)
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/*
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**test_vld2q_lane_bf16:
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** vld2.16 {d0\[2\], d2\[2\]}, \[r0\]
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** bx lr
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** ...
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** vld2.16 {d[0-9]+\[2\], d[0-9]+\[2\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x8x2_t
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test_vld2q_lane_bf16 (const bfloat16_t *a, bfloat16x8x2_t b)
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@ -30,8 +32,9 @@ test_vld2q_lane_bf16 (const bfloat16_t *a, bfloat16x8x2_t b)
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/*
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**test_vld3_lane_bf16:
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** vld3.16 {d0\[2\], d1\[2\], d2\[2\]}, \[r0\]
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** bx lr
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** ...
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** vld3.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r[0-9]+\]
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** ...
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*/
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bfloat16x4x3_t
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test_vld3_lane_bf16 (const bfloat16_t *a, bfloat16x4x3_t b)
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@ -41,8 +44,9 @@ test_vld3_lane_bf16 (const bfloat16_t *a, bfloat16x4x3_t b)
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/*
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**test_vld3q_lane_bf16:
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** vld3.16 {d0\[2\], d2\[2\], d4\[2\]}, \[r0\]
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** bx lr
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** ...
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** vld3.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r0\]
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** ...
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*/
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bfloat16x8x3_t
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test_vld3q_lane_bf16 (const bfloat16_t *a, bfloat16x8x3_t b)
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@ -52,8 +56,9 @@ test_vld3q_lane_bf16 (const bfloat16_t *a, bfloat16x8x3_t b)
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/*
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**test_vld4_lane_bf16:
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** vld4.16 {d0\[2\], d1\[2\], d2\[2\], d3\[2\]}, \[r0\]
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** bx lr
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** ...
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** vld4.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r0\]
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** ...
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*/
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bfloat16x4x4_t
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test_vld4_lane_bf16 (const bfloat16_t *a, bfloat16x4x4_t b)
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@ -63,8 +68,9 @@ test_vld4_lane_bf16 (const bfloat16_t *a, bfloat16x4x4_t b)
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/*
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**test_vld4q_lane_bf16:
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** vld4.16 {d0\[2\], d2\[2\], d4\[2\], d6\[2\]}, \[r0\]
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** bx lr
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** ...
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** vld4.16 {d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\], d[0-9]+\[2\]}, \[r0\]
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** ...
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*/
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bfloat16x8x4_t
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test_vld4q_lane_bf16 (const bfloat16_t *a, bfloat16x8x4_t b)
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@ -1,6 +1,6 @@
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/* { dg-do assemble } */
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/* { dg-require-effective-target arm_v8_2a_i8mm_ok } */
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/* { dg-options "-save-temps -O2 -march=armv8.2-a+i8mm" } */
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/* { dg-options "-save-temps -O2 -march=armv8.2-a+i8mm -mfloat-abi=hard" } */
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#include "arm_neon.h"
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