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bfin.c (hard_regno_mode_ok): Only allow first 31 regs for DImode.

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* config/bfin/bfin.c (hard_regno_mode_ok): Only allow first 31
	regs for DImode.
	(bfin_register_move_cost): Bump costs if trying to move plain
	integer values through accumulators.

From-SVN: r119055
This commit is contained in:
Bernd Schmidt 2006-11-21 12:07:39 +00:00 committed by Bernd Schmidt
parent 0eb9706479
commit 84e32cbb1f
2 changed files with 22 additions and 2 deletions
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5
gcc/ChangeLog
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@ -9,6 +9,11 @@
(add_to_reg): Renamed from add_to_sp. All callers changed. Lose some
dead code.
* config/bfin/bfin.c (hard_regno_mode_ok): Only allow first 31
regs for DImode.
(bfin_register_move_cost): Bump costs if trying to move plain
integer values through accumulators.
2006-11-21 Ben Elliston <bje@au.ibm.com>
* config/spu/spu.c (spu_expand_vector_init): Initialise x.

19
gcc/config/bfin/bfin.c
View File

@ -1854,10 +1854,16 @@ hard_regno_mode_ok (int regno, enum machine_mode mode)
return mode == BImode;
if (mode == PDImode || mode == V2PDImode)
return regno == REG_A0 || regno == REG_A1;
/* Allow all normal 32 bit regs, except REG_M3, in case regclass ever comes
up with a bad register class (such as ALL_REGS) for DImode. */
if (mode == DImode)
return regno < REG_M3;
if (mode == SImode
&& TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
return 1;
return TEST_HARD_REG_BIT (reg_class_contents[MOST_REGS], regno);
}
@ -1873,7 +1879,7 @@ bfin_vector_mode_supported_p (enum machine_mode mode)
one in class CLASS2. A cost of 2 is the default. */
int
bfin_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
bfin_register_move_cost (enum machine_mode mode,
enum reg_class class1, enum reg_class class2)
{
/* These need secondary reloads, so they're more expensive. */
@ -1891,6 +1897,15 @@ bfin_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
if (class1 == DREGS && class2 != DREGS)
return 2 * 2;
if (GET_MODE_CLASS (mode) == MODE_INT)
{
/* Discourage trying to use the accumulators. */
if (TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A0)
|| TEST_HARD_REG_BIT (reg_class_contents[class1], REG_A1)
|| TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A0)
|| TEST_HARD_REG_BIT (reg_class_contents[class2], REG_A1))
return 20;
}
return 2;
}