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[ARM/AArch64][testsuite] Add vsubw tests, putting most of the code in common with vaddw through vXXWw.inc.
2015-01-21 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from vXXXw.inc. From-SVN: r219938
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Christophe Lyon
Christophe Lyon
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@ -1,3 +1,10 @@
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2015-01-21 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/vXXXw.inc: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vsubw.c: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vaddw.c: Use code from
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vXXXw.inc.
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2015-01-21 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/vXXXl.inc: New file.
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@ -0,0 +1,70 @@
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#define FNNAME1(NAME) exec_ ## NAME
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#define FNNAME(NAME) FNNAME1(NAME)
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void FNNAME (INSN_NAME) (void)
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{
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/* Basic test: y=vaddw(x1,x2), then store the result. */
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#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
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VECT_VAR(vector_res, T1, W2, N) = \
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INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
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VECT_VAR(vector2, T1, W, N)); \
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vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
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#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
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TEST_VADDW1(INSN, T1, T2, W, W2, N)
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DECL_VARIABLE(vector, int, 16, 8);
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DECL_VARIABLE(vector, int, 32, 4);
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DECL_VARIABLE(vector, int, 64, 2);
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DECL_VARIABLE(vector, uint, 16, 8);
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DECL_VARIABLE(vector, uint, 32, 4);
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DECL_VARIABLE(vector, uint, 64, 2);
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DECL_VARIABLE(vector2, int, 8, 8);
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DECL_VARIABLE(vector2, int, 16, 4);
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DECL_VARIABLE(vector2, int, 32, 2);
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DECL_VARIABLE(vector2, uint, 8, 8);
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DECL_VARIABLE(vector2, uint, 16, 4);
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DECL_VARIABLE(vector2, uint, 32, 2);
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DECL_VARIABLE(vector_res, int, 16, 8);
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DECL_VARIABLE(vector_res, int, 32, 4);
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DECL_VARIABLE(vector_res, int, 64, 2);
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DECL_VARIABLE(vector_res, uint, 16, 8);
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DECL_VARIABLE(vector_res, uint, 32, 4);
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DECL_VARIABLE(vector_res, uint, 64, 2);
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clean_results ();
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/* Initialize input "vector" from "buffer". */
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VLOAD(vector, buffer, q, int, s, 16, 8);
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VLOAD(vector, buffer, q, int, s, 32, 4);
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VLOAD(vector, buffer, q, int, s, 64, 2);
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VLOAD(vector, buffer, q, uint, u, 16, 8);
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VLOAD(vector, buffer, q, uint, u, 32, 4);
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VLOAD(vector, buffer, q, uint, u, 64, 2);
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/* Choose init value arbitrarily. */
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VDUP(vector2, , int, s, 8, 8, -13);
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VDUP(vector2, , int, s, 16, 4, -14);
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VDUP(vector2, , int, s, 32, 2, -16);
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VDUP(vector2, , uint, u, 8, 8, 0xf3);
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VDUP(vector2, , uint, u, 16, 4, 0xfff1);
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VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
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/* Execute the tests. */
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TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
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TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
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TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
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TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
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TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
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TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
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CHECK_RESULTS (TEST_MSG, "");
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}
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int main (void)
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{
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FNNAME (INSN_NAME) ();
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return 0;
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}
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@ -2,6 +2,9 @@
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vaddw
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#define TEST_MSG "VADDW"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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@ -45,76 +48,4 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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#define INSN_NAME vaddw
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#define TEST_MSG "VADDW"
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#define FNNAME1(NAME) exec_ ## NAME
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#define FNNAME(NAME) FNNAME1(NAME)
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void FNNAME (INSN_NAME) (void)
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{
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/* Basic test: y=vaddw(x1,x2), then store the result. */
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#define TEST_VADDW1(INSN, T1, T2, W, W2, N) \
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VECT_VAR(vector_res, T1, W2, N) = \
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INSN##_##T2##W(VECT_VAR(vector, T1, W2, N), \
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VECT_VAR(vector2, T1, W, N)); \
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vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector_res, T1, W2, N))
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#define TEST_VADDW(INSN, T1, T2, W, W2, N) \
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TEST_VADDW1(INSN, T1, T2, W, W2, N)
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DECL_VARIABLE(vector, int, 16, 8);
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DECL_VARIABLE(vector, int, 32, 4);
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DECL_VARIABLE(vector, int, 64, 2);
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DECL_VARIABLE(vector, uint, 16, 8);
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DECL_VARIABLE(vector, uint, 32, 4);
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DECL_VARIABLE(vector, uint, 64, 2);
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DECL_VARIABLE(vector2, int, 8, 8);
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DECL_VARIABLE(vector2, int, 16, 4);
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DECL_VARIABLE(vector2, int, 32, 2);
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DECL_VARIABLE(vector2, uint, 8, 8);
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DECL_VARIABLE(vector2, uint, 16, 4);
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DECL_VARIABLE(vector2, uint, 32, 2);
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DECL_VARIABLE(vector_res, int, 16, 8);
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DECL_VARIABLE(vector_res, int, 32, 4);
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DECL_VARIABLE(vector_res, int, 64, 2);
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DECL_VARIABLE(vector_res, uint, 16, 8);
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DECL_VARIABLE(vector_res, uint, 32, 4);
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DECL_VARIABLE(vector_res, uint, 64, 2);
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clean_results ();
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/* Initialize input "vector" from "buffer". */
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VLOAD(vector, buffer, q, int, s, 16, 8);
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VLOAD(vector, buffer, q, int, s, 32, 4);
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VLOAD(vector, buffer, q, int, s, 64, 2);
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VLOAD(vector, buffer, q, uint, u, 16, 8);
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VLOAD(vector, buffer, q, uint, u, 32, 4);
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VLOAD(vector, buffer, q, uint, u, 64, 2);
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/* Choose init value arbitrarily. */
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VDUP(vector2, , int, s, 8, 8, -13);
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VDUP(vector2, , int, s, 16, 4, -14);
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VDUP(vector2, , int, s, 32, 2, -16);
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VDUP(vector2, , uint, u, 8, 8, 0xf3);
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VDUP(vector2, , uint, u, 16, 4, 0xfff1);
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VDUP(vector2, , uint, u, 32, 2, 0xfffffff0);
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/* Execute the tests. */
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TEST_VADDW(INSN_NAME, int, s, 8, 16, 8);
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TEST_VADDW(INSN_NAME, int, s, 16, 32, 4);
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TEST_VADDW(INSN_NAME, int, s, 32, 64, 2);
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TEST_VADDW(INSN_NAME, uint, u, 8, 16, 8);
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TEST_VADDW(INSN_NAME, uint, u, 16, 32, 4);
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TEST_VADDW(INSN_NAME, uint, u, 32, 64, 2);
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CHECK_RESULTS (TEST_MSG, "");
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}
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int main (void)
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{
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FNNAME (INSN_NAME) ();
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return 0;
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}
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#include "vXXXw.inc"
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50
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
Normal file
50
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubw.c
Normal file
@ -0,0 +1,50 @@
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vsubw
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#define TEST_MSG "VSUBW"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0xfffd, 0xfffe, 0xffff, 0x0,
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0x1, 0x2, 0x3, 0x4 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffffe, 0xffffffff, 0x0, 0x1 };
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VECT_VAR_DECL(expected,int,64,2) [] = { 0x0, 0x1 };
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VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0xfefd, 0xfefe, 0xfeff, 0xff00,
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0xff01, 0xff02, 0xff03, 0xff04 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfffeffff, 0xffff0000,
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0xffff0001, 0xffff0002 };
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VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffff00000000,
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0xffffffff00000001 };
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VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
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0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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#include "vXXXw.inc"
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