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[AArch64] Add zero_extend variants of logical+not ops

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* config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze):
	New pattern.
	(*xor_one_cmplsidi3_ze): Likewise.

From-SVN: r222263
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Kyrylo Tkachov 2015-04-21 11:24:05 +00:00 committed by Kyrylo Tkachov
parent 8a29fdfd23
commit 8409e468a5
2 changed files with 26 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2015-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (*<NLOGICAL:optab>_one_cmplsidi3_ze):
New pattern.
(*xor_one_cmplsidi3_ze): Likewise.
2015-04-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
* df-core.c (df_finish_pass): Iterate over df->problems_by_index[] and

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gcc/config/aarch64/aarch64.md
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@ -3058,6 +3058,26 @@
(set_attr "simd" "*,yes")]
)
(define_insn "*<NLOGICAL:optab>_one_cmplsidi3_ze"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "r"))))]
""
"<NLOGICAL:nlogical>\\t%w0, %w2, %w1"
[(set_attr "type" "logic_reg")]
)
(define_insn "*xor_one_cmplsidi3_ze"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(not:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")))))]
""
"eon\\t%w0, %w1, %w2"
[(set_attr "type" "logic_reg")]
)
;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)).
;; eon does not operate on SIMD registers so the vector variant must be split.
(define_insn_and_split "*xor_one_cmpl<mode>3"