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invoke.texi: Remove the MIPS -membedded-pic option.
* doc/invoke.texi: Remove the MIPS -membedded-pic option.
* config/mips/mips-protos.h (embedded_pic_fnaddr_reg): Delete.
(embedded_pic_offset): Delete.
* config/mips/mips.h (MASK_EMBEDDED_PIC): Delete. Shuffle other
MASK_* constants.
(TARGET_EMBEDDED_PIC): Delete.
(TARGET_SWITCHES): Remove -m{no-,}embedded-pic.
(ASM_SPEC): Remove -membedded-pic.
(ASM_OUTPUT_ADDR_DIFF_ELT): Remove embedded-pic handling.
(ASM_OUTPUT_CASE_LABEL): Likewise.
* config/mips/vxworks.h (ASM_SPEC): Remove -membedded-pic.
* config/mips/windiss.h (ASM_SPEC): Likewise.
* config/mips/mips.c (struct machine_function): Remove
embedded_pic_fnaddr_rtx.
(TARGET_ENCODE_SECTION_INFO): Remove override.
(embedded_pic_fnaddr_reg, embedded_pic_offset): Delete.
(override_options): Remove -membedded-pic handling.
(print_operand): Remove handling of '%S'.
(mips_select_section: Remove -membedded-pic handling.
(mips_encode_section_info): Delete.
(mips_output_conditional_branch): Remove mention of -membedded-pic.
* config/mips/mips.md (define_attr length, movsi, movdi, jump): Remove
-membedded-pic handling.
(casesi, casesi_internal, casesi_internal_di, get_fnaddr): Delete.
From-SVN: r81007
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
e930d01a4f
commit
827555ea3e
@ -1,3 +1,30 @@
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2004-04-22 Richard Sandiford <rsandifo@redhat.com>
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* doc/invoke.texi: Remove the MIPS -membedded-pic option.
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* config/mips/mips-protos.h (embedded_pic_fnaddr_reg): Delete.
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(embedded_pic_offset): Delete.
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* config/mips/mips.h (MASK_EMBEDDED_PIC): Delete. Shuffle other
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MASK_* constants.
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(TARGET_EMBEDDED_PIC): Delete.
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(TARGET_SWITCHES): Remove -m{no-,}embedded-pic.
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(ASM_SPEC): Remove -membedded-pic.
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(ASM_OUTPUT_ADDR_DIFF_ELT): Remove embedded-pic handling.
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(ASM_OUTPUT_CASE_LABEL): Likewise.
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* config/mips/vxworks.h (ASM_SPEC): Remove -membedded-pic.
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* config/mips/windiss.h (ASM_SPEC): Likewise.
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* config/mips/mips.c (struct machine_function): Remove
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embedded_pic_fnaddr_rtx.
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(TARGET_ENCODE_SECTION_INFO): Remove override.
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(embedded_pic_fnaddr_reg, embedded_pic_offset): Delete.
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(override_options): Remove -membedded-pic handling.
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(print_operand): Remove handling of '%S'.
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(mips_select_section: Remove -membedded-pic handling.
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(mips_encode_section_info): Delete.
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(mips_output_conditional_branch): Remove mention of -membedded-pic.
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* config/mips/mips.md (define_attr length, movsi, movdi, jump): Remove
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-membedded-pic handling.
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(casesi, casesi_internal, casesi_internal_di, get_fnaddr): Delete.
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2004-04-22 Alan Modra <amodra@bigpond.net.au>
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* var-tracking.c (frame_base_decl): Remove useless GTY.
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@ -117,8 +117,6 @@ extern int m16_nuimm8_4 (rtx, enum machine_mode);
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extern int m16_simm8_8 (rtx, enum machine_mode);
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extern int m16_nsimm8_8 (rtx, enum machine_mode);
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extern struct rtx_def *embedded_pic_fnaddr_reg (void);
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extern struct rtx_def *embedded_pic_offset (rtx);
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extern rtx mips_subword (rtx, int);
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extern bool mips_split_64bit_move_p (rtx, rtx);
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extern void mips_split_64bit_move (rtx, rtx);
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@ -206,7 +206,6 @@ static void mips_select_rtx_section (enum machine_mode, rtx,
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static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
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ATTRIBUTE_UNUSED;
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static bool mips_in_small_data_p (tree);
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static void mips_encode_section_info (tree, rtx, int);
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static int mips_fpr_return_fields (tree, tree *);
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static bool mips_return_in_msb (tree);
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static rtx mips_return_fpr_pair (enum machine_mode mode,
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@ -274,10 +273,6 @@ struct mips_frame_info GTY(())
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};
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struct machine_function GTY(()) {
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/* Pseudo-reg holding the address of the current function when
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generating embedded PIC code. */
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rtx embedded_pic_fnaddr_rtx;
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/* Pseudo-reg holding the value of $28 in a mips16 function which
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refers to GP relative global variables. */
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rtx mips16_gp_pseudo_rtx;
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@ -695,8 +690,6 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
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#undef TARGET_ADDRESS_COST
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#define TARGET_ADDRESS_COST mips_address_cost
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#undef TARGET_ENCODE_SECTION_INFO
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#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
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#undef TARGET_IN_SMALL_DATA_P
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#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
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@ -2444,55 +2437,6 @@ mips_address_cost (rtx addr)
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return mips_address_insns (addr, SImode);
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}
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/* Return a pseudo that points to the address of the current function.
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The first time it is called for a function, an initializer for the
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pseudo is emitted in the beginning of the function. */
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rtx
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embedded_pic_fnaddr_reg (void)
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{
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if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
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{
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rtx seq;
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cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
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/* Output code at function start to initialize the pseudo-reg. */
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/* ??? We used to do this in FINALIZE_PIC, but that does not work for
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inline functions, because it is called after RTL for the function
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has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
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does not get copied, and ends up not matching the rest of the RTL.
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This solution works, but means that we get unnecessary code to
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initialize this value every time a function is inlined into another
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function. */
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start_sequence ();
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emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
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XEXP (DECL_RTL (current_function_decl), 0)));
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seq = get_insns ();
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end_sequence ();
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push_topmost_sequence ();
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emit_insn_after (seq, get_insns ());
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pop_topmost_sequence ();
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}
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return cfun->machine->embedded_pic_fnaddr_rtx;
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}
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/* Return RTL for the offset from the current function to the argument.
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X is the symbol whose offset from the current function we want. */
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rtx
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embedded_pic_offset (rtx x)
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{
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/* Make sure it is emitted. */
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embedded_pic_fnaddr_reg ();
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return
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gen_rtx_CONST (Pmode,
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gen_rtx_MINUS (Pmode, x,
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XEXP (DECL_RTL (current_function_decl), 0)));
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}
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/* Return one word of double-word value OP, taking into account the fixed
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endianness of certain registers. HIGH_P is true to select the high part,
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false to select the low part. */
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@ -4778,30 +4722,6 @@ override_options (void)
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if (!targetm.have_named_sections)
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mips_section_threshold = 0;
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/* -membedded-pic is a form of PIC code suitable for embedded
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systems. All calls are made using PC relative addressing, and
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all data is addressed using the $gp register. This requires gas,
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which does most of the work, and GNU ld, which automatically
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expands PC relative calls which are out of range into a longer
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instruction sequence. All gcc really does differently is
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generate a different sequence for a switch. */
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if (TARGET_EMBEDDED_PIC)
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{
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flag_pic = 1;
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if (TARGET_ABICALLS)
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warning ("-membedded-pic and -mabicalls are incompatible");
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if (g_switch_set)
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warning ("-G and -membedded-pic are incompatible");
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/* Setting mips_section_threshold is not required, because gas
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will force everything to be GP addressable anyhow, but
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setting it will cause gcc to make better estimates of the
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number of instructions required to access a particular data
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item. */
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mips_section_threshold = 0x7fffffff;
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}
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/* mips_split_addresses is a half-way house between explicit
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relocations and the traditional assembler macros. It can
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split absolute 32-bit symbolic constants into a high/lo_sum
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@ -5255,7 +5175,6 @@ mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
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'F' print part of opcode for a floating-point branch condition.
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'N' print part of opcode for a branch condition, inverted.
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'W' print part of opcode for a floating-point branch condition, inverted.
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'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
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'B' print 'z' for EQ, 'n' for NE
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'b' print 'n' for EQ, 'z' for NE
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'T' print 'f' for EQ, 't' for NE
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@ -5493,14 +5412,6 @@ print_operand (FILE *file, rtx op, int letter)
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else if (letter == 'R')
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print_operand_reloc (file, op, mips_lo_relocs);
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else if (letter == 'S')
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{
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char buffer[100];
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ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
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assemble_name (file, buffer);
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}
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else if (letter == 'Z')
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{
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register int regnum;
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@ -7260,11 +7171,7 @@ static void
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mips_select_section (tree decl, int reloc,
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unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
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{
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if (TARGET_EMBEDDED_PIC && TREE_CODE (decl) == STRING_CST)
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/* For embedded position independent code, put constant strings in the
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text section, because the data section is limited to 64K in size. */
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text_section ();
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else if (targetm.have_named_sections)
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if (targetm.have_named_sections)
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default_elf_select_section (decl, reloc, align);
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else
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/* The native irix o32 assembler doesn't support named sections. */
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@ -7318,38 +7225,6 @@ mips_in_small_data_p (tree decl)
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size = int_size_in_bytes (TREE_TYPE (decl));
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return (size > 0 && size <= mips_section_threshold);
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}
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/* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
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symbols which are not in the .text section. */
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static void
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mips_encode_section_info (tree decl, rtx rtl, int first)
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{
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rtx symbol;
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if (GET_CODE (rtl) != MEM)
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return;
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symbol = XEXP (rtl, 0);
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if (GET_CODE (symbol) != SYMBOL_REF)
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return;
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if (TARGET_EMBEDDED_PIC)
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{
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if (TREE_CODE (decl) == VAR_DECL)
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SYMBOL_REF_FLAG (symbol) = 1;
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else if (TREE_CODE (decl) == FUNCTION_DECL)
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SYMBOL_REF_FLAG (symbol) = 0;
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else if (TREE_CODE (decl) == STRING_CST)
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SYMBOL_REF_FLAG (symbol) = 0;
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else
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SYMBOL_REF_FLAG (symbol) = 1;
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}
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default_encode_section_info (decl, rtl, first);
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}
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/* See whether VALTYPE is a record whose fields should be returned in
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floating-point registers. If so, return the number of fields and
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@ -8977,7 +8852,7 @@ mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
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.set macro
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.set reorder
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When generating non-embedded PIC, instead of:
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When generating PIC, instead of:
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j target
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@ -154,24 +154,23 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define MASK_XGOT 0x00000800 /* emit big-got PIC */
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#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
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#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
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#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
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#define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
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#define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
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#define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
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#define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
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#define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
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#define MASK_MIPS16 0x00100000 /* Generate mips16 code */
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#define MASK_EMBEDDED_DATA 0x00004000 /* Reduce RAM usage, not fast code */
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#define MASK_BIG_ENDIAN 0x00008000 /* Generate big endian code */
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#define MASK_SINGLE_FLOAT 0x00010000 /* Only single precision FPU. */
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#define MASK_MAD 0x00020000 /* Generate mad/madu as on 4650. */
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#define MASK_4300_MUL_FIX 0x00040000 /* Work-around early Vr4300 CPU bug */
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#define MASK_MIPS16 0x00080000 /* Generate mips16 code */
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#define MASK_NO_CHECK_ZERO_DIV \
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0x00200000 /* divide by zero checking */
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#define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
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0x00100000 /* divide by zero checking */
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#define MASK_BRANCHLIKELY 0x00200000 /* Generate Branch Likely
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instructions. */
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#define MASK_UNINIT_CONST_IN_RODATA \
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0x00800000 /* Store uninitialized
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0x00400000 /* Store uninitialized
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consts in rodata */
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#define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */
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#define MASK_FIX_R4400 0x02000000 /* Work around R4400 errata. */
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#define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */
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#define MASK_FIX_VR4120 0x08000000 /* Work around VR4120 errata. */
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#define MASK_FIX_R4000 0x00800000 /* Work around R4000 errata. */
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#define MASK_FIX_R4400 0x01000000 /* Work around R4400 errata. */
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#define MASK_FIX_SB1 0x02000000 /* Work around SB-1 errata. */
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#define MASK_FIX_VR4120 0x04000000 /* Work around VR4120 errata. */
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#define MASK_FP_EXCEPTIONS 0x10000000 /* FP exceptions are enabled. */
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@ -220,10 +219,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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/* always call through a register */
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#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
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/* generate embedded PIC code;
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requires gas. */
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#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
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/* for embedded systems, optimize for
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reduced RAM space instead of for
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fastest code. */
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@ -567,10 +562,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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N_("Use indirect calls")}, \
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{"no-long-calls", -MASK_LONG_CALLS, \
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N_("Don't use indirect calls")}, \
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{"embedded-pic", MASK_EMBEDDED_PIC, \
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N_("Use embedded PIC")}, \
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{"no-embedded-pic", -MASK_EMBEDDED_PIC, \
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N_("Don't use embedded PIC")}, \
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{"embedded-data", MASK_EMBEDDED_DATA, \
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N_("Use ROM instead of RAM")}, \
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{"no-embedded-data", -MASK_EMBEDDED_DATA, \
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@ -1130,7 +1121,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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%{mfix-vr4120} \
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%(subtarget_asm_optimizing_spec) \
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%(subtarget_asm_debugging_spec) \
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%{membedded-pic} \
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%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
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%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
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%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
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@ -3213,19 +3203,15 @@ while (0)
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LOCAL_LABEL_PREFIX, \
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VALUE)
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/* This is how to output an element of a case-vector that is relative.
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This is used for pc-relative code (e.g. when TARGET_ABICALLS or
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TARGET_EMBEDDED_PIC). */
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/* This is how to output an element of a case-vector. We can make the
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entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
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is supported. */
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#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
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do { \
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if (TARGET_MIPS16) \
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fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
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LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
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else if (TARGET_EMBEDDED_PIC) \
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fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
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ptr_mode == DImode ? ".dword" : ".word", \
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LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
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else if (TARGET_GPWORD) \
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fprintf (STREAM, "\t%s\t%sL%d\n", \
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ptr_mode == DImode ? ".gpdword" : ".gpword", \
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@ -3236,16 +3222,15 @@ do { \
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LOCAL_LABEL_PREFIX, VALUE); \
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} while (0)
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/* When generating embedded PIC or mips16 code we want to put the jump
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table in the .text section. In all other cases, we want to put the
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jump table in the .rdata section. Unfortunately, we can't use
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JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
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Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
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section if appropriate. */
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/* When generating mips16 code we want to put the jump table in the .text
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section. In all other cases, we want to put the jump table in the .rdata
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section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
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it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
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to the .text section if appropriate. */
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#undef ASM_OUTPUT_CASE_LABEL
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#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
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do { \
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if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
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if (TARGET_MIPS16) \
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function_section (current_function_decl); \
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(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
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} while (0)
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@ -173,8 +173,7 @@
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(cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
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(const_int 131072))
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(const_int 4)
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(ne (symbol_ref "flag_pic && ! TARGET_EMBEDDED_PIC")
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||||
(const_int 0))
|
||||
(ne (symbol_ref "flag_pic") (const_int 0))
|
||||
(const_int 24)
|
||||
] (const_int 12))
|
||||
|
||||
@ -4519,23 +4518,6 @@ dsrl\t%3,%3,1\n\
|
||||
{
|
||||
if (mips_legitimize_move (DImode, operands[0], operands[1]))
|
||||
DONE;
|
||||
|
||||
/* If we are generating embedded PIC code, and we are referring to a
|
||||
symbol in the .text section, we must use an offset from the start
|
||||
of the function. */
|
||||
if (TARGET_EMBEDDED_PIC
|
||||
&& (GET_CODE (operands[1]) == LABEL_REF
|
||||
|| (GET_CODE (operands[1]) == SYMBOL_REF
|
||||
&& ! SYMBOL_REF_FLAG (operands[1]))))
|
||||
{
|
||||
rtx temp;
|
||||
|
||||
temp = embedded_pic_offset (operands[1]);
|
||||
temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
|
||||
force_reg (DImode, temp));
|
||||
emit_move_insn (operands[0], force_reg (DImode, temp));
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
||||
;; For mips16, we need a special case to handle storing $31 into
|
||||
@ -4663,23 +4645,6 @@ dsrl\t%3,%3,1\n\
|
||||
{
|
||||
if (mips_legitimize_move (SImode, operands[0], operands[1]))
|
||||
DONE;
|
||||
|
||||
/* If we are generating embedded PIC code, and we are referring to a
|
||||
symbol in the .text section, we must use an offset from the start
|
||||
of the function. */
|
||||
if (TARGET_EMBEDDED_PIC
|
||||
&& (GET_CODE (operands[1]) == LABEL_REF
|
||||
|| (GET_CODE (operands[1]) == SYMBOL_REF
|
||||
&& ! SYMBOL_REF_FLAG (operands[1]))))
|
||||
{
|
||||
rtx temp;
|
||||
|
||||
temp = embedded_pic_offset (operands[1]);
|
||||
temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
|
||||
force_reg (SImode, temp));
|
||||
emit_move_insn (operands[0], force_reg (SImode, temp));
|
||||
DONE;
|
||||
}
|
||||
})
|
||||
|
||||
;; We can only store $ra directly into a small sp offset.
|
||||
@ -8091,7 +8056,7 @@ srl\t%M0,%M1,%2\n\
|
||||
(label_ref (match_operand 0 "" "")))]
|
||||
"!TARGET_MIPS16"
|
||||
{
|
||||
if (flag_pic && ! TARGET_EMBEDDED_PIC)
|
||||
if (flag_pic)
|
||||
{
|
||||
if (get_attr_length (insn) <= 8)
|
||||
return "%*b\t%l0%/";
|
||||
@ -8107,12 +8072,11 @@ srl\t%M0,%M1,%2\n\
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
(set (attr "length")
|
||||
;; we can't use `j' when emitting non-embedded PIC, so we emit
|
||||
;; branch, if it's in range, or load the address of the branch
|
||||
;; target into $at in a PIC-compatible way and then jump to it.
|
||||
;; We can't use `j' when emitting PIC. Emit a branch if it's
|
||||
;; in range, otherwise load the address of the branch target into
|
||||
;; $at and then jump to it.
|
||||
(if_then_else
|
||||
(ior (eq (symbol_ref "flag_pic && ! TARGET_EMBEDDED_PIC")
|
||||
(const_int 0))
|
||||
(ior (eq (symbol_ref "flag_pic") (const_int 0))
|
||||
(lt (abs (minus (match_dup 0)
|
||||
(plus (pc) (const_int 4))))
|
||||
(const_int 131072)))
|
||||
@ -8247,107 +8211,6 @@ srl\t%M0,%M1,%2\n\
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Implement a switch statement when generating embedded PIC code.
|
||||
;; Switches are implemented by `tablejump' when not using -membedded-pic.
|
||||
|
||||
(define_expand "casesi"
|
||||
[(set (match_dup 5)
|
||||
(minus:SI (match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "const_int_operand" "")))
|
||||
(set (cc0)
|
||||
(compare:CC (match_dup 5)
|
||||
(match_operand:SI 2 "arith_operand" "")))
|
||||
(set (pc)
|
||||
(if_then_else (gtu (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 4 "" ""))
|
||||
(pc)))
|
||||
(parallel
|
||||
[(set (pc)
|
||||
(mem:SI (plus:SI (mult:SI (match_dup 5)
|
||||
(const_int 4))
|
||||
(label_ref (match_operand 3 "" "")))))
|
||||
(clobber (match_scratch:SI 6 ""))
|
||||
(clobber (reg:SI 31))])]
|
||||
"TARGET_EMBEDDED_PIC"
|
||||
{
|
||||
rtx index;
|
||||
|
||||
/* If the index is too large, go to the default label. */
|
||||
index = expand_binop (SImode, sub_optab, operands[0],
|
||||
operands[1], 0, 0, OPTAB_WIDEN);
|
||||
emit_insn (gen_cmpsi (index, operands[2]));
|
||||
emit_insn (gen_bgtu (operands[4]));
|
||||
|
||||
/* Do the PIC jump. */
|
||||
if (Pmode != DImode)
|
||||
emit_jump_insn (gen_casesi_internal (index, operands[3],
|
||||
gen_reg_rtx (SImode)));
|
||||
else
|
||||
emit_jump_insn (gen_casesi_internal_di (index, operands[3],
|
||||
gen_reg_rtx (DImode)));
|
||||
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; An embedded PIC switch statement looks like this:
|
||||
;; bal $LS1
|
||||
;; sll $reg,$index,2
|
||||
;; $LS1:
|
||||
;; addu $reg,$reg,$31
|
||||
;; lw $reg,$L1-$LS1($reg)
|
||||
;; addu $reg,$reg,$31
|
||||
;; j $reg
|
||||
;; $L1:
|
||||
;; .word case1-$LS1
|
||||
;; .word case2-$LS1
|
||||
;; ...
|
||||
|
||||
(define_insn "casesi_internal"
|
||||
[(set (pc)
|
||||
(mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
|
||||
(const_int 4))
|
||||
(label_ref (match_operand 1 "" "")))))
|
||||
(clobber (match_operand:SI 2 "register_operand" "=d"))
|
||||
(clobber (reg:SI 31))]
|
||||
"TARGET_EMBEDDED_PIC"
|
||||
{
|
||||
if (set_nomacro)
|
||||
return "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
|
||||
.set macro\;lw\\t%2,%1-%S1(%2)\;.set nomacro\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/";
|
||||
return
|
||||
"%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
|
||||
lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
||||
;
|
||||
}
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "24")])
|
||||
|
||||
;; This code assumes that the table index will never be >= 29 bits wide,
|
||||
;; which allows the 'sign extend' from SI to DI be a no-op.
|
||||
(define_insn "casesi_internal_di"
|
||||
[(set (pc)
|
||||
(mem:DI (plus:DI (sign_extend:DI
|
||||
(mult:SI (match_operand:SI 0 "register_operand" "d")
|
||||
(const_int 8)))
|
||||
(label_ref (match_operand 1 "" "")))))
|
||||
(clobber (match_operand:DI 2 "register_operand" "=d"))
|
||||
(clobber (reg:DI 31))]
|
||||
"TARGET_EMBEDDED_PIC"
|
||||
{
|
||||
if (set_nomacro)
|
||||
return "%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
|
||||
.set macro\;ld\\t%2,%1-%S1(%2)\;.set nomacro\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/";
|
||||
return
|
||||
"%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
|
||||
ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
||||
;
|
||||
}
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "24")])
|
||||
|
||||
;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
|
||||
;; While it is possible to either pull it off the stack (in the
|
||||
;; o32 case) or recalculate it given t9 and our target label,
|
||||
@ -8461,20 +8324,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
;; When generating embedded PIC code we need to get the address of the
|
||||
;; current function. This specialized instruction does just that.
|
||||
|
||||
(define_insn "get_fnaddr"
|
||||
[(set (match_operand 0 "register_operand" "=d")
|
||||
(unspec [(match_operand 1 "" "")] UNSPEC_GET_FNADDR))
|
||||
(clobber (reg:SI 31))]
|
||||
"TARGET_EMBEDDED_PIC
|
||||
&& GET_CODE (operands[1]) == SYMBOL_REF"
|
||||
"%($LF%= = . + 8\;bal\t$LF%=\;nop;la\t%0,%1-$LF%=%)\;addu\t%0,%0,$31"
|
||||
[(set_attr "type" "call")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "20")])
|
||||
|
||||
;; This is used in compiling the unwind routines.
|
||||
(define_expand "eh_return"
|
||||
[(use (match_operand 0 "general_operand" ""))]
|
||||
|
||||
@ -45,7 +45,6 @@ Boston, MA 02111-1307, USA. */
|
||||
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
|
||||
%(subtarget_asm_optimizing_spec) \
|
||||
%(subtarget_asm_debugging_spec) \
|
||||
%{membedded-pic} \
|
||||
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
|
||||
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
|
||||
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
|
||||
|
||||
@ -45,7 +45,6 @@ Boston, MA 02111-1307, USA. */
|
||||
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
|
||||
%(subtarget_asm_optimizing_spec) \
|
||||
%(subtarget_asm_debugging_spec) \
|
||||
%{membedded-pic} \
|
||||
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
|
||||
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
|
||||
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
|
||||
|
||||
@ -468,9 +468,9 @@ in the following sections.
|
||||
@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
|
||||
-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
|
||||
-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
|
||||
-mxgot -mno-xgot -membedded-pic -mno-embedded-pic @gol
|
||||
-mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol
|
||||
-msingle-float -mdouble-float -mint64 -mlong64 -mlong32 @gol
|
||||
-mxgot -mno-xgot -mgp32 -mgp64 -mfp32 -mfp64 @gol
|
||||
-mhard-float -msoft-float -msingle-float -mdouble-float @gol
|
||||
-mint64 -mlong64 -mlong32 @gol
|
||||
-G@var{num} -membedded-data -mno-embedded-data @gol
|
||||
-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
|
||||
-msplit-addresses -mno-split-addresses @gol
|
||||
@ -7924,16 +7924,6 @@ file accesses more than 64k's worth of GOT entries. Very few do.
|
||||
These options have no effect unless GCC is generating position
|
||||
independent code.
|
||||
|
||||
@item -membedded-pic
|
||||
@itemx -mno-embedded-pic
|
||||
@opindex membedded-pic
|
||||
@opindex mno-embedded-pic
|
||||
Generate (do not generate) position-independent code suitable for some
|
||||
embedded systems. All calls are made using PC relative addresses, and
|
||||
all data is addressed using the $gp register. No more than 65536
|
||||
bytes of global data may be used. This requires GNU as and GNU ld,
|
||||
which do most of the work.
|
||||
|
||||
@item -mgp32
|
||||
@opindex mgp32
|
||||
Assume that general-purpose registers are 32 bits wide.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user