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pa.md (addvdi3, [...]): New ftrapv insns and expanders.
* pa.md (addvdi3, addvsi3, subvdi3, subvsi3, negvdi2, negvsi2): New ftrapv insns and expanders. (subdi3): Change define_expand operand 1 to arith11_operand, and operand 2 to reg_or_0_operand. Change constraints of 64-bit insn pattern to handle reg_or_0 operands. Revise 32-bit insn pattern to handle 11-bit constants and reg_or_0 operands in operands 1 and 2, respectively. From-SVN: r121552
This commit is contained in:
John David Anglin
John David Anglin
parent
2e3e8cea38
commit
7fcc8dcf4a
@ -1,5 +1,13 @@
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2007-02-03 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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* pa.md (addvdi3, addvsi3, subvdi3, subvsi3, negvdi2, negvsi2): New
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ftrapv insns and expanders.
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(subdi3): Change define_expand operand 1 to arith11_operand, and
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operand 2 to reg_or_0_operand. Change constraints of 64-bit insn
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pattern to handle reg_or_0 operands. Revise 32-bit insn pattern to
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handle 11-bit constants and reg_or_0 operands in operands 1 and 2,
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respectively.
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PR middle-end/30174
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* varasm.c (notice_global_symbol): Treat global objects as weak when
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flag_shlib is true.
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@ -5349,6 +5349,59 @@
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[(set_attr "type" "binary")
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(set_attr "length" "4")])
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(define_expand "addvdi3"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
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(match_operand:DI 2 "arith11_operand" "")))
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(trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (plus:DI (match_dup 1)
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(match_dup 2))))
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(const_int 0))])]
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""
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"")
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
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(match_operand:DI 2 "arith11_operand" "r,I")))
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(trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (plus:DI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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"TARGET_64BIT"
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"@
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add,tsv,* %2,%1,%0
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addi,tsv,* %2,%1,%0"
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[(set_attr "type" "binary,binary")
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(set_attr "length" "4,4")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
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(match_operand:DI 2 "arith11_operand" "rI")))
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(trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (plus:DI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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"!TARGET_64BIT"
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT)
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{
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if (INTVAL (operands[2]) >= 0)
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return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
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else
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return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
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}
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else
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return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
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}"
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[(set_attr "type" "binary")
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(set_attr "length" "8")])
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;; define_splits to optimize cases of adding a constant integer
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;; to a register when the constant does not fit in 14 bits. */
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(define_split
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@ -5426,26 +5479,33 @@
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(set_attr "pa_combine_type" "addmove")
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(set_attr "length" "4,4")])
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(define_insn "addvsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
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(match_operand:SI 2 "arith11_operand" "r,I")))
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(trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2)))
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(sign_extend:DI (plus:SI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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""
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"@
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{addo|add,tsv} %2,%1,%0
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{addio|addi,tsv} %2,%1,%0"
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[(set_attr "type" "binary,binary")
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(set_attr "length" "4,4")])
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(define_expand "subdi3"
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[(set (match_operand:DI 0 "register_operand" "")
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(minus:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "register_operand" "")))]
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(minus:DI (match_operand:DI 1 "arith11_operand" "")
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(match_operand:DI 2 "reg_or_0_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "register_operand" "r")))]
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"!TARGET_64BIT"
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"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
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[(set_attr "type" "binary")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,r,!q")
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(minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
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(match_operand:DI 2 "register_operand" "r,r,!r")))]
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(match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
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"TARGET_64BIT"
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"@
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sub %1,%2,%0
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@ -5454,6 +5514,91 @@
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[(set_attr "type" "binary,binary,move")
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(set_attr "length" "4,4,4")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,&r")
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(minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
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(match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
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"!TARGET_64BIT"
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"*
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{
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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if (INTVAL (operands[1]) >= 0)
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return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
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else
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return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
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}
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else
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return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
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}"
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[(set_attr "type" "binary")
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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(const_int 8)
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(if_then_else (ge (symbol_ref "INTVAL (operands[1])")
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(const_int 0))
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(const_int 8)
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(const_int 12))))])
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(define_expand "subvdi3"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(minus:DI (match_operand:DI 1 "arith11_operand" "")
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(match_operand:DI 2 "reg_or_0_operand" "")))
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(trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (minus:DI (match_dup 1)
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(match_dup 2))))
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(const_int 0))])]
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""
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"")
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
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(match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
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(trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (minus:DI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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"TARGET_64BIT"
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"@
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{subo|sub,tsv} %1,%2,%0
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{subio|subi,tsv} %1,%2,%0"
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[(set_attr "type" "binary,binary")
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(set_attr "length" "4,4")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,&r")
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(minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
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(match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
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(trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (minus:DI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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"!TARGET_64BIT"
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"*
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{
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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if (INTVAL (operands[1]) >= 0)
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return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
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else
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return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
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}
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else
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return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
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}"
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[(set_attr "type" "binary,binary")
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(set (attr "length")
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(if_then_else (eq_attr "alternative" "0")
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(const_int 8)
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(if_then_else (ge (symbol_ref "INTVAL (operands[1])")
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(const_int 0))
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(const_int 8)
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(const_int 12))))])
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(define_expand "subsi3"
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[(set (match_operand:SI 0 "register_operand" "")
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(minus:SI (match_operand:SI 1 "arith11_operand" "")
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@ -5484,6 +5629,22 @@
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[(set_attr "type" "binary,binary,move")
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(set_attr "length" "4,4,4")])
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(define_insn "subvsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
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(match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
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(trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2)))
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(sign_extend:DI (minus:SI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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""
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"@
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{subo|sub,tsv} %1,%2,%0
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{subio|subi,tsv} %1,%2,%0"
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[(set_attr "type" "binary,binary")
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(set_attr "length" "4,4")])
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;; Clobbering a "register_operand" instead of a match_scratch
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;; in operand3 of millicode calls avoids spilling %r1 and
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;; produces better code.
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@ -6031,6 +6192,37 @@
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[(set_attr "type" "unary")
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(set_attr "length" "4")])
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(define_expand "negvdi2"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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(neg:DI (match_operand:DI 1 "register_operand" "")))
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(trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
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(sign_extend:TI (neg:DI (match_dup 1))))
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(const_int 0))])]
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""
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"")
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(neg:DI (match_operand:DI 1 "register_operand" "r")))
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(trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
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(sign_extend:TI (neg:DI (match_dup 1))))
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(const_int 0))]
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"!TARGET_64BIT"
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"sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "8")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(neg:DI (match_operand:DI 1 "register_operand" "r")))
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(trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
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(sign_extend:TI (neg:DI (match_dup 1))))
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(const_int 0))]
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"TARGET_64BIT"
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"sub,tsv %%r0,%1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "4")])
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "register_operand" "r")))]
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@ -6039,6 +6231,17 @@
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[(set_attr "type" "unary")
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(set_attr "length" "4")])
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(define_insn "negvsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "register_operand" "r")))
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(trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
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(sign_extend:DI (neg:SI (match_dup 1))))
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(const_int 0))]
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""
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"{subo|sub,tsv} %%r0,%1,%0"
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[(set_attr "type" "unary")
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(set_attr "length" "4")])
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(define_expand "one_cmpldi2"
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[(set (match_operand:DI 0 "register_operand" "")
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(not:DI (match_operand:DI 1 "register_operand" "")))]
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