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rs6000.c (rs6000_legitimize_address): Check for non-word-aligned REG+CONST addressing.

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gcc/

	* config/rs6000/rs6000.c (rs6000_legitimize_address): Check for
	non-word-aligned REG+CONST addressing.

gcc/testsuite/

	* gcc.c-torture/compile/20090107-1.c: New test.


Co-Authored-By: Alan Modra <amodra@bigpond.net.au>

From-SVN: r143171
This commit is contained in:
Nathan Froyd 2009-01-07 23:21:26 +00:00 committed by Nathan Froyd
parent c4bca01b27
commit 7da13f1d80
4 changed files with 40 additions and 1 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2009-01-07 Nathan Froyd <froydnj@codesourcery.com>
Alan Modra <amodra@bigpond.net.au>
* config/rs6000/rs6000.c (rs6000_legitimize_address): Check for
non-word-aligned REG+CONST addressing.
2009-01-07 Uros Bizjak <ubizjak@gmail.com>
PR target/38706

5
gcc/config/rs6000/rs6000.c
View File

@ -3804,7 +3804,10 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_CODE (XEXP (x, 0)) == REG
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
&& !(SPE_VECTOR_MODE (mode)
&& !((TARGET_POWERPC64
&& (mode == DImode || mode == TImode)
&& (INTVAL (XEXP (x, 1)) & 3) != 0)
|| SPE_VECTOR_MODE (mode)
|| ALTIVEC_VECTOR_MODE (mode)
|| (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
|| mode == DImode || mode == DDmode

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2009-01-07 Nathan Froyd <froydnj@codesourcery.com>
Alan Modra <amodra@bigpond.net.au>
* gcc.c-torture/compile/20090107-1.c: New test.
2009-01-07 Uros Bizjak <ubizjak@gmail.com>
PR target/38706

25
gcc/testsuite/gcc.c-torture/compile/20090107-1.c Normal file
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@ -0,0 +1,25 @@
/* Verify that we don't ICE by forming invalid addresses for unaligned
doubleword loads (originally for PPC64). */
struct a
{
unsigned int x;
unsigned short y;
} __attribute__((packed));
struct b {
struct a rep;
unsigned long long seq;
} __attribute__((packed));
struct c {
int x;
struct a a[5460];
struct b b;
};
extern void use_ull(unsigned long long);
extern void f(struct c *i) {
use_ull(i->b.seq);
return;
}