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h8300.h (FIRST_PSEUDO_REGISTER): Bump up by one.
* h8300/h8300.h (FIRST_PSEUDO_REGISTER): Bump up by one.
(ARG_POINTER_REGNUM): Likewise.
(FIXED_REGISTERS): Add entry for MAC register.
(CALL_USED_REGISTERS< REG_ALLOC_ORDER): Likewise.
(HARD_REGNO_NREGS): Handle MAC register.
(HARD_REGNO_MODE_OK< REGNO_OK_FOR_BASE_P): LIkewise.
(REGISTER_NAMES): Likewise.
(enum reg_class): New MAC_REGS register class.
(REG_CLASS_CONTENTS, REGNO_REG_CLASS): Corresponding changes.
(REG_CLASS_FROM_LETTER): LIkewise.
(REGISTER_MOVE_COST): Make copies to/from the MAC register
expenseive.
(CONDITIONAL_REGISTER_USAGE): Define.
* h8300/h8300.md (movsi_h8300hs): Renamed from movsi_h8300h.
Handle moves to/from the MAC register.
(mac): Two new patterns to use the mac instruction.
* h8300/h8300.c (notice_update_cc): Fix CC_SET case.
(restore_compare_p): Remove unused function.
* h8300/h8300.md: Handle "set" vs "set_zn_c0" correctly.
(bCC patterns): No longer need to call restore_compare_p.
* h8300/h8300.c (get_shift_alg): Fix HImode ASHIFTRT by
13 or 14 bits.
From-SVN: r12848
This commit is contained in:
Jeff Law
parent
725de644d6
commit
7d9f07f4f9
@ -1574,11 +1574,10 @@ notice_update_cc (body, insn)
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break;
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case CC_SET:
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/* Insn sets the Z,N flags of CC to recog_operand[0].
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V is always set to 0. C may or may not be set to 0 but that's ok
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/* Insn sets the Z,N,V flags of CC to recog_operand[0].
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C may or may not be set to 0 but that's ok
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because alter_cond will change tests to use EQ/NE. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY;
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cc_status.value1 = recog_operand[0];
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break;
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@ -1604,44 +1603,6 @@ notice_update_cc (body, insn)
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}
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}
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/* Return 1 if a previous compare needs to be re-issued. This will happen
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if the compare was deleted because the previous insn set it, but the
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branch needs CC flags not set.
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OP is the comparison being performed. */
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int
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restore_compare_p (op)
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rtx op;
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{
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switch (GET_CODE (op))
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{
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case EQ:
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case NE:
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break;
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case LT:
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case LE:
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case GT:
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case GE:
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if (cc_status.flags & CC_OVERFLOW_UNUSABLE)
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return 1;
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break;
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case LTU:
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case LEU:
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case GTU:
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case GEU:
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/* If the carry flag isn't usable, the test should have been changed
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by alter_cond. */
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if (cc_status.flags & CC_NO_CARRY)
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abort ();
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break;
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default:
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abort ();
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}
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return 0;
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}
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/* Recognize valid operators for bit instructions */
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int
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@ -2329,7 +2290,7 @@ get_shift_alg (cpu, shift_type, mode, count, assembler_p,
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*cc_valid_p = 0;
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return SHIFT_SPECIAL;
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}
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else
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else if (shift_type != SHIFT_ASHIFTRT)
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{
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*assembler_p = rotate_one[cpu][shift_type][shift_mode];
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if (TARGET_H8300S)
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@ -229,18 +229,18 @@ do { \
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All registers that the compiler knows about must be given numbers,
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even those that are not normally considered general registers.
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Reg 8 does not correspond to any hardware register, but instead
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Reg 9 does not correspond to any hardware register, but instead
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appears in the RTL as an argument pointer prior to reload, and is
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eliminated during reloading in favor of either the stack or frame
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pointer. */
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#define FIRST_PSEUDO_REGISTER 9
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#define FIRST_PSEUDO_REGISTER 10
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/* 1 for registers that have pervasive standard uses
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and are not available for the register allocator. */
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#define FIXED_REGISTERS \
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{ 0, 0, 0, 0, 0, 0, 0, 1, 1}
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{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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@ -253,19 +253,28 @@ do { \
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h8 destroys r0,r1,r2,r3. */
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#define CALL_USED_REGISTERS \
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{ 1, 1, 1, 1, 0, 0, 0, 1, 1 }
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{ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1 }
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#define REG_ALLOC_ORDER \
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{ 2, 3, 0, 1, 4, 5, 6, 7, 8}
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{ 2, 3, 0, 1, 4, 5, 6, 8, 7, 9}
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#define CONDITIONAL_REGISTER_USAGE \
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{ \
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if (!TARGET_H8300S) \
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fixed_regs[8] = call_used_regs[8] = 1;\
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}
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/* Return number of consecutive hard regs needed starting at reg REGNO
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to hold something of mode MODE.
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This is ordinarily the length in words of a value of mode MODE
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but can be less for certain modes in special long registers. */
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but can be less for certain modes in special long registers.
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We pretend the MAC register is 32bits -- we don't have any data
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types on the H8 series to handle more than 32bits. */
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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/* Value is 1 if hard register REGNO can hold a value of machine-mode
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MODE.
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@ -276,7 +285,7 @@ do { \
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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(TARGET_H8300 ? (((REGNO)&1)==0) || (MODE==HImode) || (MODE==QImode) \
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: 1)
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: REGNO == 8 ? MODE == SImode : 1)
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/* Value is 1 if it is a good idea to tie two pseudo registers
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when one has mode MODE1 and one has mode MODE2.
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@ -304,7 +313,7 @@ do { \
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#define FRAME_POINTER_REQUIRED 0
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM 8
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#define ARG_POINTER_REGNUM 9
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/* Register in which static-chain is passed to a function. */
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#define STATIC_CHAIN_REGNUM 3
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@ -330,7 +339,7 @@ do { \
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class that represents their union. */
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enum reg_class {
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NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
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NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
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};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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@ -338,7 +347,7 @@ enum reg_class {
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/* Give names of register classes as strings for dump file. */
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#define REG_CLASS_NAMES \
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{ "NO_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
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{ "NO_REGS", "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
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/* Define which registers fit in which classes.
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This is an initializer for a vector of HARD_REG_SET
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@ -347,26 +356,27 @@ enum reg_class {
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#define REG_CLASS_CONTENTS \
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{ 0, /* No regs */ \
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0x0ff, /* GENERAL_REGS */ \
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0x1ff, /* ALL_REGS */ \
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0x100, /* MAC_REGS */ \
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0x3ff, /* ALL_REGS */ \
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}
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/* The same information, inverted:
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Return the class number of the smallest class containing
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reg number REGNO. This could be a conditional expression
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or could index an array.
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or could index an array. */
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??? What about the ARG_POINTER_REGISTER? */
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#define REGNO_REG_CLASS(REGNO) GENERAL_REGS
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#define REGNO_REG_CLASS(REGNO) (REGNO != 8 ? GENERAL_REGS : MAC_REGS)
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/* The class value for index registers, and the one for base regs. */
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#define INDEX_REG_CLASS NO_REGS
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#define BASE_REG_CLASS GENERAL_REGS
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/* Get reg_class from a letter such as appears in the machine description. */
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/* Get reg_class from a letter such as appears in the machine description.
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#define REG_CLASS_FROM_LETTER(C) (NO_REGS)
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'a' is the MAC register. */
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#define REG_CLASS_FROM_LETTER(C) ((C) == 'a' ? MAC_REGS : NO_REGS)
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/* The letters I, J, K, L, M, N, O, P in a register constraint string
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can be used to stand for particular ranges of immediate operands.
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@ -422,7 +432,8 @@ enum reg_class {
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so define REGISTER_MOVE_COST to be > 2 so that reload never
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shortcuts. */
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) 3
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
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(CLASS1 == MAC_REGS || CLASS2 == MAC_REGS ? 6 : 3)
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/* Stack layout; function entry, exit and calling. */
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@ -731,7 +742,7 @@ struct rtx_def *function_arg();
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#define REGNO_OK_FOR_INDEX_P(regno) 0
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#define REGNO_OK_FOR_BASE_P(regno) \
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((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
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(((regno) < FIRST_PSEUDO_REGISTER && regno != 8) || reg_renumber[regno] >= 0)
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/* Maximum number of registers that can appear in a valid memory address. */
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@ -1140,7 +1151,7 @@ readonly_data() \
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This sequence is indexed by compiler's hard-register-number (see above). */
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#define REGISTER_NAMES \
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "ap"}
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "mac", "ap"}
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#define ADDITIONAL_REGISTER_NAMES { { "r7", 7 } }
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@ -86,7 +86,7 @@
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;; none_0hit - insn does not affect cc but it does modify operand 0
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;; This attribute is used to keep track of when operand 0 changes.
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;; See the description of NOTICE_UPDATE_CC for more info.
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;; set - insn sets flags z,n. v,c are set to 0.
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;; set - insn sets flags z,n,v. c are set to 0.
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;; (c may not really be set to 0 but that's ok, we don't need it anyway).
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;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
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;; be known (if it isn't that's ok, we don't need it anyway).
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@ -113,7 +113,7 @@
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return \"push.l %S1\";
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}"
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[(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn_c0")])
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(define_insn ""
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[(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
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@ -131,7 +131,7 @@
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[(const_int 2) (const_int 2) (const_int 2) (const_int 2)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set_zn_c0,set,set,set,set,set")])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand_dst" "")
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@ -159,7 +159,7 @@
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[(set_attr_alternative "length"
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[(const_int 2) (const_int 2) (const_int 2)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set_zn_c0,set,set,set")])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")])
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;; movhi
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@ -177,7 +177,7 @@
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return \"push.l %S1\";
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}"
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[(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn_c0")])
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(define_insn ""
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[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
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@ -195,7 +195,7 @@
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[(const_int 2) (const_int 2) (const_int 2) (const_int 4)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set_zn_c0,set,set,set,set,set")])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand_dst" "")
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@ -223,7 +223,7 @@
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[(set_attr_alternative "length"
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[(const_int 2) (const_int 2) (const_int 4)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set_zn_c0,set,set,set")])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")])
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;; movsi
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@ -395,16 +395,22 @@
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[(set_attr "length" "4,4,8,8,4,4")
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(set_attr "cc" "clobber")])
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(define_insn "movsi_h8300h"
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[(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r")
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(match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>"))]
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"(TARGET_H8300H || TARGET_H8300S)
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(define_insn "movsi_h8300hs"
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[(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r,*a,*a,r")
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(match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>,I,r,*a"))]
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"(TARGET_H8300S || TARGET_H8300H)
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&& (register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode))"
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"*
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{
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if (which_alternative == 0)
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return \"sub.l %S0,%S0\";
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if (which_alternative == 6)
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return \"clrmac\";
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if (which_alternative == 7)
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return \"clrmac\;ldmac %1,macl\";
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if (which_alternative == 8)
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return \"stmac macl,%0\";
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if (GET_CODE (operands[1]) == CONST_INT)
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{
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int val = INTVAL (operands[1]);
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@ -433,8 +439,8 @@
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}
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return \"mov.l %S1,%S0\";
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}"
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[(set_attr "length" "2,2,10,10,4,4")
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(set_attr "cc" "set_zn_c0,set,set,set,set,set")])
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[(set_attr "length" "2,2,10,10,4,4,2,6,4")
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,none_0hit,none_0hit,set_zn_c0")])
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(define_insn "movsf_h8300h"
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[(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
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@ -450,7 +456,7 @@
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mov.l %S1,%S0
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mov.l %S1,%S0"
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[(set_attr "length" "2,2,10,10,4,4")
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(set_attr "cc" "set_zn_c0,set,set,set,set,set")])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
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;; ----------------------------------------------------------------------
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;; TEST INSTRUCTIONS
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@ -515,21 +521,21 @@
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""
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"mov.b %X0,%X0"
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[(set_attr "length" "2")
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn_c0")])
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(define_insn "tsthi"
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[(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
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""
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"mov.w %T0,%T0"
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[(set_attr "length" "2")
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn_c0")])
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(define_insn "tstsi"
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[(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
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"TARGET_H8300H || TARGET_H8300S"
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"mov.l %S0,%S0"
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[(set_attr "length" "2")
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn_c0")])
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(define_insn "cmpqi"
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[(set (cc0)
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@ -591,7 +597,7 @@
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""
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"add.b %X2,%X0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set")])
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(define_expand "addhi3"
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[(set (match_operand:HI 0 "register_operand" "")
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@ -625,7 +631,7 @@
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add.w %T2,%T0
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mov.w %T1,%T0\;add.w %T2,%T0"
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[(set_attr "length" "4,2,6")
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(set_attr "cc" "clobber,set_zn_c0,set_zn_c0")])
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(set_attr "cc" "clobber,set,set")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r,r")
|
||||
@ -636,7 +642,7 @@
|
||||
add.w %T2,%T0
|
||||
add.w %T2,%T0"
|
||||
[(set_attr "length" "4,2")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set,set")])
|
||||
|
||||
(define_expand "addsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
@ -681,7 +687,7 @@
|
||||
add.l %S2,%S0
|
||||
add.l %S2,%S0"
|
||||
[(set_attr "length" "6,2")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set,set")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; SUBTRACT INSTRUCTIONS
|
||||
@ -696,7 +702,7 @@
|
||||
sub.b %X2,%X0
|
||||
add.b %G2,%X0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set")])
|
||||
|
||||
(define_expand "subhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "")
|
||||
@ -734,7 +740,7 @@
|
||||
sub.w %T2,%T0
|
||||
add.b %E2,%s0\;addx %F2,%t0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,clobber")])
|
||||
(set_attr "cc" "set,clobber")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,&r")
|
||||
@ -745,7 +751,7 @@
|
||||
sub.w %T2,%T0
|
||||
sub.w %T2,%T0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set,set")])
|
||||
|
||||
(define_expand "subsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
@ -792,7 +798,7 @@
|
||||
sub.l %S2,%S0
|
||||
sub.l %S2,%S0"
|
||||
[(set_attr "length" "2,6")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set,set")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; MULTIPLY INSTRUCTIONS
|
||||
@ -836,6 +842,38 @@
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "none_0hit")])
|
||||
|
||||
;; This is a "bridge" instruction. Combine can't cram enough insns
|
||||
;; together to crate a MAC instruction directly, but it can create
|
||||
;; this instruction, which then allows combine to create the real
|
||||
;; MAC insn.
|
||||
;;
|
||||
;; Unfortunately, if combine doesn't create a MAC instruction, this
|
||||
;; insn must generate reasonably correct code. Egad.
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
|
||||
(sign_extend:SI
|
||||
(mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
|
||||
"TARGET_H8300S"
|
||||
"clrmac\;mac %2,%1"
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "cc" "none_0hit")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
||||
(plus (mult:SI
|
||||
(sign_extend:SI (mem:HI
|
||||
(post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
|
||||
(sign_extend:SI (mem:HI
|
||||
(post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
|
||||
(match_operand:SI 3 "register_operand" "0")))]
|
||||
"TARGET_H8300S"
|
||||
"mac %2,%1"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "none_0hit")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; DIVIDE INSTRUCTIONS
|
||||
;; ----------------------------------------------------------------------
|
||||
@ -947,7 +985,7 @@
|
||||
and %X2,%X0
|
||||
bclr %W2,%R0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,none_0hit")])
|
||||
(set_attr "cc" "set_zn_c0,none_0hit")])
|
||||
|
||||
(define_expand "andqi3"
|
||||
[(set (match_operand:QI 0 "bit_operand" "")
|
||||
@ -1051,7 +1089,7 @@
|
||||
or %X2,%X0
|
||||
bset %V2,%R0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,none_0hit")])
|
||||
(set_attr "cc" "set_zn_c0,none_0hit")])
|
||||
|
||||
(define_expand "iorqi3"
|
||||
[(set (match_operand:QI 0 "bit_operand" "=r,U")
|
||||
@ -1137,7 +1175,7 @@
|
||||
xor %X2,%X0
|
||||
bnot %V2,%R0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,none_0hit")])
|
||||
(set_attr "cc" "set_zn_c0,none_0hit")])
|
||||
|
||||
(define_expand "xorqi3"
|
||||
[(set (match_operand:QI 0 "bit_operand" "=r,U")
|
||||
@ -1292,7 +1330,7 @@
|
||||
""
|
||||
"not %X0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
(define_insn "one_cmplhi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -1436,11 +1474,6 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
/* If we erroneously deleted a compare insn (which can happen if we need
|
||||
CC bits set that aren't), emit the compare. */
|
||||
if (restore_compare_p (operands[1]))
|
||||
return 0;
|
||||
|
||||
if (get_attr_length (insn) == 2)
|
||||
return \"b%j1 %l0\";
|
||||
else if (get_attr_length (insn) == 4)
|
||||
@ -1460,11 +1493,6 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
/* If we erroneously deleted a compare insn (which can happen if we need
|
||||
CC bits set that aren't), emit the compare. */
|
||||
if (restore_compare_p (operands[1]))
|
||||
return 0;
|
||||
|
||||
if (get_attr_length (insn) == 2)
|
||||
return \"b%k1 %l0\";
|
||||
else if (get_attr_length (insn) == 4)
|
||||
@ -1661,7 +1689,7 @@
|
||||
extu.l %S0
|
||||
mov.w %T1,%T0\;extu.l %S0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,set")])
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
|
||||
(define_expand "extendqihi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "")
|
||||
@ -1687,7 +1715,7 @@
|
||||
exts.w %T0
|
||||
mov.b %R1,%s0\;exts.w %T0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,set")])
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
|
||||
;; The compiler can synthesize a 300H variant of this which is
|
||||
;; just as efficient as one that we'd create
|
||||
@ -1744,7 +1772,7 @@
|
||||
exts.l %S0
|
||||
mov.w %T1,%T0\;exts.l %S0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,set")])
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; SHIFTS
|
||||
@ -2214,7 +2242,7 @@
|
||||
"(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
|
||||
"mov.w @(%u4,%T1),%T0"
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
|
||||
@ -2226,7 +2254,7 @@
|
||||
"(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
|
||||
"mov.w %T0,@(%u4,%T1)"
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
;; Notice a move which could be post incremented.
|
||||
|
||||
@ -2237,7 +2265,7 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.b @%T1+,%X0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:HI 0 "register_operand" "")
|
||||
@ -2246,7 +2274,7 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.w @%T1+,%T0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
;; Notice a move which could be predecremented.
|
||||
|
||||
@ -2258,7 +2286,7 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.b %X0,@-%T1"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:HI 1 "register_operand" "")
|
||||
@ -2268,5 +2296,5 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.w %T0,@-%T1"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set")])
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user