re PR target/19005 (Error: bad register name `%sil')

PR target/19005
        * config/i386/i386.md (swaphi_1): Swap with swaphi_2, allow with
        optimize_size.
        (swapqi_1): Rename from swapqi.  Enable only for no partial reg
        stall and optimize_size.
        (swapqi_2): New.
        (swaphi_1, swaphi_2, swapqi_1): Add athlon_decode.
        (swapsi, swaphi_1, swaphi_2, swapqi_1, swapdi): Remove modrm override.

From-SVN: r92250
This commit is contained in:
Richard Henderson 2004-12-16 01:40:31 -08:00
parent 692308bbd4
commit 7cc6af0cda
2 changed files with 41 additions and 21 deletions

View File

@ -1,3 +1,14 @@
2004-12-15 Richard Henderson <rth@redhat.com>
PR target/19005
* config/i386/i386.md (swaphi_1): Swap with swaphi_2, allow with
optimize_size.
(swapqi_1): Rename from swapqi. Enable only for no partial reg
stall and optimize_size.
(swapqi_2): New.
(swaphi_1, swaphi_2, swapqi_1): Add athlon_decode.
(swapsi, swaphi_1, swaphi_2, swapqi_1, swapdi): Remove modrm override.
2004-12-16 Uros Bizjak <uros@kss-loka.si>
* config/i386/i386.md (*floathisf2_i387, *floathidf2_i387):
@ -57,13 +68,13 @@
on the STMT_EXPR wrapping up the inlined body.
2004-12-15 Vladimir Makarov <vmakarov@redhat.com>
Steven Bosscher <stevenb@suse.de>
Steven Bosscher <stevenb@suse.de>
PR middle end/17340
* global.c: Update comments in a few places.
(check_earlyclobber): Return true if there are early clobber
classes.
(calculate_local_reg_bb_info): Do not try to mark earlyclobber
(calculate_local_reg_bb_info): Do not try to mark earlyclobber
regs if there are none.
(bb_info, allocate_bb_info, free_bb_info, modify_reg_pav,
make_accurate_live_analysis): Rename pavin, pavout to live_pavin,

View File

@ -1238,10 +1238,9 @@
""
"xchg{l}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "mode" "SI")
(set_attr "modrm" "0")])
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_expand "movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
@ -1355,24 +1354,24 @@
(match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
"TARGET_PARTIAL_REG_STALL"
"xchg{w}\t%1, %0"
"!TARGET_PARTIAL_REG_STALL || optimize_size"
"xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
(set_attr "mode" "SI")
(set_attr "pent_pair" "np")
(set_attr "mode" "HI")
(set_attr "modrm" "0")])
(set_attr "athlon_decode" "vector")])
(define_insn "*swaphi_2"
[(set (match_operand:HI 0 "register_operand" "+r")
(match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
"! TARGET_PARTIAL_REG_STALL"
"xchg{l}\t%k1, %k0"
"TARGET_PARTIAL_REG_STALL"
"xchg{w}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "mode" "HI")
(set_attr "pent_pair" "np")
(set_attr "mode" "SI")
(set_attr "modrm" "0")])
(set_attr "athlon_decode" "vector")])
(define_expand "movstricthi"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
@ -1521,17 +1520,29 @@
DONE;
})
(define_insn "*swapqi"
(define_insn "*swapqi_1"
[(set (match_operand:QI 0 "register_operand" "+r")
(match_operand:QI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
""
"!TARGET_PARTIAL_REG_STALL || optimize_size"
"xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
(set_attr "mode" "SI")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_insn "*swapqi_2"
[(set (match_operand:QI 0 "register_operand" "+q")
(match_operand:QI 1 "register_operand" "+q"))
(set (match_dup 1)
(match_dup 0))]
"TARGET_PARTIAL_REG_STALL"
"xchg{b}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "mode" "QI")
(set_attr "modrm" "0")])
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_expand "movstrictqi"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
@ -2094,12 +2105,10 @@
"TARGET_64BIT"
"xchg{q}\t%1, %0"
[(set_attr "type" "imov")
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")
(set_attr "mode" "DI")
(set_attr "modrm" "0")])
(set_attr "pent_pair" "np")
(set_attr "athlon_decode" "vector")])
(define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "general_operand" ""))]