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re PR rtl-optimization/53352 (Incorrect CSE optimization on RTL expressions with a paradoxical subreg)

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gcc/
2012-05-15  Meador Inge  <meadori@codesourcery.com>

	PR rtl-optimization/53352
	* cse.c (equiv_constant): Ignore paradoxical subregs.

gcc/testsuite/
2012-05-15  Meador Inge  <meadori@codesourcery.com>

	PR rtl-optimization/53352
	* gcc.dg/pr53352.c: New test.

From-SVN: r187648
This commit is contained in:
Meador Inge 2012-05-18 09:04:38 +00:00 committed by Richard Sandiford
parent 4a3afb1a3d
commit 7cb6668a1f
4 changed files with 56 additions and 1 deletions

5
gcc/ChangeLog

@ -1,3 +1,8 @@
2012-05-18 Meador Inge <meadori@codesourcery.com>
PR rtl-optimization/53352
* cse.c (equiv_constant): Ignore paradoxical subregs.
2012-05-17 Steven Bosscher <steven@gcc.gnu.org>
PR rtl-optimization/53125

6
gcc/cse.c

@ -3786,8 +3786,12 @@ equiv_constant (rtx x)
}
}
/* Otherwise see if we already have a constant for the inner REG. */
/* Otherwise see if we already have a constant for the inner REG,
and if that is enough to calculate an equivalent constant for
the subreg. Note that the upper bits of paradoxical subregs
are undefined, so they cannot be said to equal anything. */
if (REG_P (SUBREG_REG (x))
&& GET_MODE_SIZE (mode) <= GET_MODE_SIZE (imode)
&& (new_rtx = equiv_constant (SUBREG_REG (x))) != 0)
return simplify_subreg (mode, new_rtx, imode, SUBREG_BYTE (x));

5
gcc/testsuite/ChangeLog

@ -1,3 +1,8 @@
2012-05-18 Meador Inge <meadori@codesourcery.com>
PR rtl-optimization/53352
* gcc.dg/pr53352.c: New test.
2012-05-17 David S. Miller <davem@davemloft.net>
* gfortran.dg/bessel_7.f90: Bump allowed precision to avoid

41
gcc/testsuite/gcc.dg/pr53352.c Normal file

@ -0,0 +1,41 @@
/* { dg-do run } */
/* { dg-options "-O1" } */
#include <stdlib.h>
typedef union
{
struct
{
unsigned char a;
unsigned char b;
unsigned char c;
unsigned char d;
} parts;
unsigned long whole;
} T;
T *g_t;
void bar (unsigned long x)
{
if (x != 0)
abort ();
}
int main ()
{
T one;
T two;
T tmp1, tmp2;
one.whole = 0xFFE0E0E0UL;
two.whole = 0xFF000000UL;
tmp1.parts = two.parts;
tmp2.parts = one.parts;
tmp2.parts.c = tmp1.parts.c;
one.parts = tmp2.parts;
g_t = &one;
bar (0);
}