ieeefp.h: Add x86-64 support.

2002-07-19  Bo Thorsen  <bo@berlioz.suse.de>

        * java/lang/ieeefp.h: Add x86-64 support.
        * configure.in: Likewise.
        * configure.host: Likewise.
        * configure: Regenerated.
        * sysdep/x86-64/locks.h: New file with x86-64 locks.

From-SVN: r55588

libjava/ChangeLog

@@ -1,3 +1,11 @@
+2002-07-19  Bo Thorsen  <bo@berlioz.suse.de>
+
+	* java/lang/ieeefp.h: Add x86-64 support.
+	* configure.in: Likewise.
+	* configure.host: Likewise.
+	* configure: Regenerated.
+	* sysdep/x86-64/locks.h: New file with x86-64 locks.
+
 2002-07-16  Mark Wielaard  <mark@klomp.org>
 
 	* java/io/StreamTokenizer.java (pushBack): Update documentation.

libjava/configure.host

@@ -85,6 +85,16 @@ case "${host}" in
 	enable_hash_synchronization_default=yes
 	slow_pthread_self=yes
 	;;
+  x86_64-*)
+	sysdeps_dir=x86-64
+	libgcj_flags="${libgcj_flags} -ffloat-store"
+	libgcj_interpreter=no
+	libgcj_cxxflags="-D__NO_MATH_INLINES"
+	libgcj_cflags="-D__NO_MATH_INLINES"
+	DIVIDESPEC=-fno-use-divide-subroutine
+	enable_hash_synchronization_default=yes
+	slow_pthread_self=yes
+	;;
   alpha*-*)
 	sysdeps_dir=alpha
 	libgcj_flags="${libgcj_flags} -mieee"
@@ -127,7 +137,8 @@ case "${host}" in
   alpha*-linux* | \
   s390*-linux* | \
   sparc*-linux* | \
-  ia64-*)
+  ia64-* | \
+  x86_64*-linux*)
   	can_unwind_signal=yes
 	;;
   *-*-darwin*)

libjava/configure.in

@@ -914,6 +914,9 @@ case "${host}" in
  s390*-*-linux*)
     SIGNAL_HANDLER=include/s390-signal.h
     ;;
+ x86_64*-*-linux*)
+    SIGNAL_HANDLER=include/dwarf2-signal.h
+    ;;
  sparc*-*-linux*)
     SIGNAL_HANDLER=include/dwarf2-signal.h
     ;;

libjava/include/dwarf2-signal.h

@@ -209,6 +209,9 @@ do								\
 while (0)  
 #endif
 #elif !defined(__ia64__)
+#if defined(__x86_64__)
+#define SYS_sigaction SYS_rt_sigaction
+#endif
 #define INIT_SEGV						\
 do								\
   {								\

libjava/java/lang/ieeefp.h

@@ -58,6 +58,10 @@
 #define __IEEE_LITTLE_ENDIAN
 #endif
 
+#ifdef __x86_64__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
 #ifdef __i960__
 #define __IEEE_LITTLE_ENDIAN
 #endif

libjava/sysdep/x86-64/locks.h

@@ -0,0 +1,74 @@
+/* locks.h - Thread synchronization primitives. x86-64 implementation.
+
+   Copyright (C) 2002  Free Software Foundation
+
+   Contributed by Bo Thorsen <bo@suse.de>.
+
+   This file is part of libgcj.
+
+This software is copyrighted work licensed under the terms of the
+Libgcj License.  Please consult the file "LIBGCJ_LICENSE" for
+details.  */
+
+#ifndef __SYSDEP_LOCKS_H__
+#define __SYSDEP_LOCKS_H__
+
+typedef size_t obj_addr_t;	/* Integer type big enough for object	*/
+				/* address.				*/
+
+// Atomically replace *addr by new_val if it was initially equal to old.
+// Return true if the comparison succeeded.
+// Assumed to have acquire semantics, i.e. later memory operations
+// cannot execute before the compare_and_swap finishes.
+inline static bool
+compare_and_swap(volatile obj_addr_t *addr, obj_addr_t old, obj_addr_t new_val)
+{
+  char result;
+  __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1"
+	      : "+m"(*(addr)), "=q"(result)
+	      : "r" (new_val), "a"(old)
+	      : "memory");
+  return (bool) result;
+}
+
+// Set *addr to new_val with release semantics, i.e. making sure
+// that prior loads and stores complete before this
+// assignment.
+// On x86-64, the hardware shouldn't reorder reads and writes,
+// so we just have to convince gcc not to do it either.
+inline static void
+release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
+{
+  __asm__ __volatile__(" " : : : "memory");
+  *(addr) = new_val;
+}
+
+// Compare_and_swap with release semantics instead of acquire semantics.
+// On many architecture, the operation makes both guarantees, so the
+// implementation can be the same.
+inline static bool
+compare_and_swap_release(volatile obj_addr_t *addr,
+			 obj_addr_t old,
+			 obj_addr_t new_val)
+{
+  return compare_and_swap(addr, old, new_val);
+}
+
+// Ensure that subsequent instructions do not execute on stale
+// data that was loaded from memory before the barrier.
+// On x86-64, the hardware ensures that reads are properly ordered.
+inline static void
+read_barrier()
+{
+}
+
+// Ensure that prior stores to memory are completed with respect to other
+// processors.
+inline static void
+write_barrier()
+{
+  /* x86-64 does not reorder writes. We just need to ensure that gcc also
+     doesn't.  */
+  __asm__ __volatile__(" " : : : "memory");
+}
+#endif