diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 758dcac4aedd..a8f28a2f1acb 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -3737,7 +3737,7 @@ fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fcmov")]) -(define_expand "maxdf3" +(define_expand "smaxdf3" [(set (match_dup 3) (le:DF (match_operand:DF 1 "reg_or_0_operand" "") (match_operand:DF 2 "reg_or_0_operand" ""))) @@ -3750,7 +3750,7 @@ operands[4] = CONST0_RTX (DFmode); }) -(define_expand "mindf3" +(define_expand "smindf3" [(set (match_dup 3) (lt:DF (match_operand:DF 1 "reg_or_0_operand" "") (match_operand:DF 2 "reg_or_0_operand" ""))) @@ -3763,7 +3763,7 @@ operands[4] = CONST0_RTX (DFmode); }) -(define_expand "maxsf3" +(define_expand "smaxsf3" [(set (match_dup 3) (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) @@ -3776,7 +3776,7 @@ operands[4] = CONST0_RTX (DFmode); }) -(define_expand "minsf3" +(define_expand "sminsf3" [(set (match_dup 3) (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 9331d90b2e1c..90b1cc599213 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -2586,7 +2586,7 @@ "fnegabs %0 = %1" [(set_attr "itanium_class" "fmisc")]) -(define_insn "minsf3" +(define_insn "sminsf3" [(set (match_operand:SF 0 "fr_register_operand" "=f") (smin:SF (match_operand:SF 1 "fr_register_operand" "f") (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] @@ -2594,7 +2594,7 @@ "fmin %0 = %1, %F2" [(set_attr "itanium_class" "fmisc")]) -(define_insn "maxsf3" +(define_insn "smaxsf3" [(set (match_operand:SF 0 "fr_register_operand" "=f") (smax:SF (match_operand:SF 1 "fr_register_operand" "f") (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] @@ -3000,7 +3000,7 @@ "fnegabs %0 = %1" [(set_attr "itanium_class" "fmisc")]) -(define_insn "mindf3" +(define_insn "smindf3" [(set (match_operand:DF 0 "fr_register_operand" "=f") (smin:DF (match_operand:DF 1 "fr_register_operand" "f") (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] @@ -3008,7 +3008,7 @@ "fmin %0 = %1, %F2" [(set_attr "itanium_class" "fmisc")]) -(define_insn "maxdf3" +(define_insn "smaxdf3" [(set (match_operand:DF 0 "fr_register_operand" "=f") (smax:DF (match_operand:DF 1 "fr_register_operand" "f") (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] @@ -3556,7 +3556,7 @@ "fnegabs %0 = %F1" [(set_attr "itanium_class" "fmisc")]) -(define_insn "minxf3" +(define_insn "sminxf3" [(set (match_operand:XF 0 "fr_register_operand" "=f") (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] @@ -3564,7 +3564,7 @@ "fmin %0 = %F1, %F2" [(set_attr "itanium_class" "fmisc")]) -(define_insn "maxxf3" +(define_insn "smaxxf3" [(set (match_operand:XF 0 "fr_register_operand" "=f") (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index fd2fbe5637f4..988dc4b8a978 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4709,7 +4709,7 @@ ;; fsel instruction and some auxiliary computations. Then we just have a ;; single DEFINE_INSN for fsel and the define_splits to make them if made by ;; combine. -(define_expand "maxsf3" +(define_expand "smaxsf3" [(set (match_operand:SF 0 "gpc_reg_operand" "") (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") (match_operand:SF 2 "gpc_reg_operand" "")) @@ -4718,7 +4718,7 @@ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") -(define_expand "minsf3" +(define_expand "sminsf3" [(set (match_operand:SF 0 "gpc_reg_operand" "") (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") (match_operand:SF 2 "gpc_reg_operand" "")) @@ -4983,7 +4983,7 @@ ;; The conditional move instructions allow us to perform max and min ;; operations even when -(define_expand "maxdf3" +(define_expand "smaxdf3" [(set (match_operand:DF 0 "gpc_reg_operand" "") (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") (match_operand:DF 2 "gpc_reg_operand" "")) @@ -4992,7 +4992,7 @@ "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") -(define_expand "mindf3" +(define_expand "smindf3" [(set (match_operand:DF 0 "gpc_reg_operand" "") (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") (match_operand:DF 2 "gpc_reg_operand" "")) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 2c41bc41c598..1f321a377c80 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2834,25 +2834,24 @@ means of constraints requiring operands 1 and 0 to be the same location. @cindex @code{udiv@var{m}3} instruction pattern @cindex @code{mod@var{m}3} instruction pattern @cindex @code{umod@var{m}3} instruction pattern -@cindex @code{smin@var{m}3} instruction pattern -@cindex @code{smax@var{m}3} instruction pattern @cindex @code{umin@var{m}3} instruction pattern @cindex @code{umax@var{m}3} instruction pattern @cindex @code{and@var{m}3} instruction pattern @cindex @code{ior@var{m}3} instruction pattern @cindex @code{xor@var{m}3} instruction pattern @item @samp{sub@var{m}3}, @samp{mul@var{m}3} -@itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3} -@itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3} +@itemx @samp{div@var{m}3}, @samp{udiv@var{m}3} +@itemx @samp{mod@var{m}3}, @samp{umod@var{m}3} +@itemx @samp{umin@var{m}3}, @samp{umax@var{m}3} @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} Similar, for other arithmetic operations. + @cindex @code{min@var{m}3} instruction pattern @cindex @code{max@var{m}3} instruction pattern -@itemx @samp{min@var{m}3}, @samp{max@var{m}3} -Floating point min and max operations. If both operands are zeros, -or if either operand is NaN, then it is unspecified which of the two -operands is returned as the result. - +@item @samp{smin@var{m}3}, @samp{smax@var{m}3} +Signed minimum and maximum operations. When used with floating point, +if both operands are zeros, or if either operand is @code{NaN}, then +it is unspecified which of the two operands is returned as the result. @cindex @code{mulhisi3} instruction pattern @item @samp{mulhisi3} diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi index 9d6b9c28a3d1..1244c74c92e0 100644 --- a/gcc/doc/rtl.texi +++ b/gcc/doc/rtl.texi @@ -1887,7 +1887,10 @@ the quotient. @item (smin:@var{m} @var{x} @var{y}) @itemx (smax:@var{m} @var{x} @var{y}) Represents the smaller (for @code{smin}) or larger (for @code{smax}) of -@var{x} and @var{y}, interpreted as signed integers in mode @var{m}. +@var{x} and @var{y}, interpreted as signed values in mode @var{m}. +When used with floating point, if both operands are zeros, or if either +operand is @code{NaN}, then it is unspecified which of the two operands +is returned as the result. @findex umin @findex umax diff --git a/gcc/genopinit.c b/gcc/genopinit.c index 72593a62ede9..61f039328d58 100644 --- a/gcc/genopinit.c +++ b/gcc/genopinit.c @@ -1,6 +1,6 @@ /* Generate code to initialize optabs from machine description. Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2002, 2003, 2004 Free Software Foundation, Inc. + 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GCC. @@ -102,10 +102,8 @@ static const char * const optabs[] = "lshr_optab->handlers[$A].insn_code = CODE_FOR_$(lshr$a3$)", "rotl_optab->handlers[$A].insn_code = CODE_FOR_$(rotl$a3$)", "rotr_optab->handlers[$A].insn_code = CODE_FOR_$(rotr$a3$)", - "smin_optab->handlers[$A].insn_code = CODE_FOR_$(smin$I$a3$)", - "smin_optab->handlers[$A].insn_code = CODE_FOR_$(min$F$a3$)", - "smax_optab->handlers[$A].insn_code = CODE_FOR_$(smax$I$a3$)", - "smax_optab->handlers[$A].insn_code = CODE_FOR_$(max$F$a3$)", + "smin_optab->handlers[$A].insn_code = CODE_FOR_$(smin$a3$)", + "smax_optab->handlers[$A].insn_code = CODE_FOR_$(smax$a3$)", "umin_optab->handlers[$A].insn_code = CODE_FOR_$(umin$I$a3$)", "umax_optab->handlers[$A].insn_code = CODE_FOR_$(umax$I$a3$)", "pow_optab->handlers[$A].insn_code = CODE_FOR_$(pow$a3$)", diff --git a/gcc/rtl.def b/gcc/rtl.def index 8ef471f98458..8acb0f40b269 100644 --- a/gcc/rtl.def +++ b/gcc/rtl.def @@ -444,11 +444,8 @@ DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) /* Bitwise operations. */ DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) - DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) - DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) - DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) /* Operand: @@ -462,7 +459,10 @@ DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ /* Minimum and maximum values of two operands. We need both signed and unsigned forms. (We cannot use MIN for SMIN because it conflicts - with a macro of the same name.) */ + with a macro of the same name.) The signed variants should be used + with floating point. Further, if both operands are zeros, or if either + operand is NaN, then it is unspecified which of the two operands is + returned as the result. */ DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) diff --git a/gcc/tree.def b/gcc/tree.def index a03f2bbb8fa1..370250dc616c 100644 --- a/gcc/tree.def +++ b/gcc/tree.def @@ -650,6 +650,9 @@ DEFTREECODE (FLOAT_EXPR, "float_expr", tcc_unary, 1) /* Unary negation. */ DEFTREECODE (NEGATE_EXPR, "negate_expr", tcc_unary, 1) +/* Minimum and maximum values. When used with floating point, if both + operands are zeros, or if either operand is NaN, then it is unspecified + which of the two operands is returned as the result. */ DEFTREECODE (MIN_EXPR, "min_expr", tcc_binary, 2) DEFTREECODE (MAX_EXPR, "max_expr", tcc_binary, 2)