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re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)
PR target/51244 * config/sh/sh.md: Add negc extu sequence peephole. (movrt, movnegt, movrt_negc, nott): Use t_reg_operand predicate. (*movrt_negc): New insn. * config/sh/sync.md (atomic_test_and_set): Pass gen_t_reg_rtx to gen_movnegt. * config/sh/sh.c (expand_cbranchsi4, sh_emit_scc_to_t, sh_emit_compare_and_branch, sh_emit_compare_and_set): Use get_t_reg_rtx. (sh_expand_t_scc): Pass gen_t_reg_rtx to gen_movnegt. PR target/51244 * gcc.target/sh/pr51244-5: New. * gcc.target/sh/pr51244-6: New. From-SVN: r190258
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Oleg Endo
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@ -1,3 +1,15 @@
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2012-08-09 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/51244
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* config/sh/sh.md: Add negc extu sequence peephole.
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(movrt, movnegt, movrt_negc, nott): Use t_reg_operand predicate.
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(*movrt_negc): New insn.
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* config/sh/sync.md (atomic_test_and_set): Pass gen_t_reg_rtx to
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gen_movnegt.
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* config/sh/sh.c (expand_cbranchsi4, sh_emit_scc_to_t,
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sh_emit_compare_and_branch, sh_emit_compare_and_set): Use get_t_reg_rtx.
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(sh_expand_t_scc): Pass gen_t_reg_rtx to gen_movnegt.
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2012-08-09 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/50751
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@ -1893,7 +1893,7 @@ expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int probability)
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branch_expander = gen_branch_false;
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default: ;
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}
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emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, T_REG),
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emit_insn (gen_rtx_SET (VOIDmode, get_t_reg_rtx (),
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gen_rtx_fmt_ee (comparison, SImode,
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operands[1], operands[2])));
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jump = emit_jump_insn (branch_expander (operands[3], get_t_reg_rtx ()));
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@ -2129,7 +2129,7 @@ sh_emit_set_t_insn (rtx insn, enum machine_mode mode)
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void
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sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
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{
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rtx t_reg = gen_rtx_REG (SImode, T_REG);
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rtx t_reg = get_t_reg_rtx ();
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enum rtx_code oldcode = code;
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enum machine_mode mode;
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@ -2304,7 +2304,7 @@ sh_emit_compare_and_branch (rtx *operands, enum machine_mode mode)
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}
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insn = gen_rtx_SET (VOIDmode,
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gen_rtx_REG (SImode, T_REG),
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get_t_reg_rtx (),
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gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
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sh_emit_set_t_insn (insn, mode);
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@ -2369,9 +2369,9 @@ sh_emit_compare_and_set (rtx *operands, enum machine_mode mode)
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if (lab)
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emit_label (lab);
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if (invert)
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emit_insn (gen_movnegt (operands[0]));
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emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
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else
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emit_move_insn (operands[0], gen_rtx_REG (SImode, T_REG));
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emit_move_insn (operands[0], get_t_reg_rtx ());
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}
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/* Functions to output assembly code. */
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@ -12121,7 +12121,7 @@ sh_expand_t_scc (rtx operands[])
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if ((code == EQ && val == 1) || (code == NE && val == 0))
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emit_insn (gen_movt (result, get_t_reg_rtx ()));
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else if ((code == EQ && val == 0) || (code == NE && val == 1))
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emit_insn (gen_movnegt (result));
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emit_insn (gen_movnegt (result, get_t_reg_rtx ()));
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else if (code == EQ || code == NE)
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emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
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else
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@ -9641,7 +9641,7 @@ label:
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(define_insn "movrt"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(xor:SI (reg:SI T_REG) (const_int 1)))]
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(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
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"TARGET_SH2A"
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"movrt %0"
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[(set_attr "type" "arith")])
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@ -9794,28 +9794,66 @@ label:
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(define_expand "movnegt"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(xor:SI (reg:SI T_REG) (const_int 1)))]
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""
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(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
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"TARGET_SH1"
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{
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if (TARGET_SH2A)
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emit_insn (gen_movrt (operands[0]));
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emit_insn (gen_movrt (operands[0], operands[1]));
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else
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{
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rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
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emit_insn (gen_movrt_negc (operands[0], val));
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emit_insn (gen_movrt_negc (operands[0], operands[1], val));
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}
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DONE;
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})
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(define_insn "movrt_negc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(xor:SI (reg:SI T_REG) (const_int 1)))
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(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
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(set (reg:SI T_REG) (const_int 1))
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(use (match_operand:SI 1 "arith_reg_operand" "r"))]
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(use (match_operand:SI 2 "arith_reg_operand" "r"))]
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"TARGET_SH1"
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"negc %1,%0"
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"negc %2,%0"
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[(set_attr "type" "arith")])
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;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
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;; pattern can be used by the combine pass. Using a scratch reg for the
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;; -1 constant results in slightly better register allocations compared to
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;; generating a pseudo reg before reload.
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(define_insn_and_split "*movrt_negc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
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(clobber (match_scratch:SI 2 "=r"))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1 && ! TARGET_SH2A"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (const_int -1))
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(parallel
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[(set (match_dup 0) (xor:SI (match_dup 1) (const_int 1)))
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(set (reg:SI T_REG) (const_int 1))
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(use (match_dup 2))])])
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;; In some cases the zero extension does not get combined away and a
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;; sequence like the following might remain:
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;; mov #-1,r2
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;; tst r1,r1
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;; negc r2,r1
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;; extu.b r1,r1
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(define_peephole2
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[(parallel
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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(xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))
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(set (reg:SI T_REG) (const_int 1))
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(use (match_operand:SI 2 "arith_reg_operand" ""))])
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(set (match_dup 0)
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(zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
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"TARGET_SH1 && REGNO (operands[0]) == REGNO (operands[3])"
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[(parallel
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[(set (match_dup 0) (xor:SI (match_dup 1) (const_int 1)))
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(set (reg:SI T_REG) (const_int 1))
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(use (match_dup 2))])])
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;; The *negnegt pattern helps the combine pass to figure out how to fold
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;; an explicit double T bit negation.
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(define_insn_and_split "*negnegt"
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@ -9855,7 +9893,8 @@ label:
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[(const_int 0)])
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(define_insn_and_split "nott"
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[(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
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[(set (reg:SI T_REG)
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(xor:SI (match_operand:SI 0 "t_reg_operand" "") (const_int 1)))]
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"TARGET_SH1"
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{
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gcc_assert (TARGET_SH2A);
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@ -830,7 +830,7 @@
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/* The result of the test op is the inverse of what we are
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supposed to return. Thus invert the T bit. The inversion will be
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potentially optimized away and integrated into surrounding code. */
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emit_insn (gen_movnegt (operands[0]));
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emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
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DONE;
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})
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@ -1,3 +1,9 @@
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2012-08-09 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/51244
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* gcc.target/sh/pr51244-5: New.
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* gcc.target/sh/pr51244-6: New.
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2012-08-09 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* gcc.target/i386/adx-addxcarry32-3.c: New.
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50
gcc/testsuite/gcc.target/sh/pr51244-5.c
Normal file
50
gcc/testsuite/gcc.target/sh/pr51244-5.c
Normal file
@ -0,0 +1,50 @@
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/* Check that no unnecessary sign or zero extension insn is generated after
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a negc or movrt insn that stores the inverted T bit in a reg. */
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/* { dg-do compile { target "sh*-*-*" } } */
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/* { dg-options "-O2" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
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/* { dg-final { scan-assembler-not "extu|exts" } } */
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int
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test_00 (int a, int b, int* c, short* d, int x)
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{
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*d = x != 0;
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*c = -1;
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if (x != 0)
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return a > 0;
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return 0;
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}
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unsigned char
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test_01 (int x)
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{
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if (x < 58 && x > 47)
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return 1;
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return 0;
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}
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char
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test_02 (int x)
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{
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if (x < 58 && x > 47)
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return 1;
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return 0;
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}
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unsigned short
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test_03 (int x)
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{
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if (x < 58 && x > 47)
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return 1;
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return 0;
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}
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short
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test_04 (int x)
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{
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if (x < 58 && x > 47)
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return 1;
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return 0;
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}
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15
gcc/testsuite/gcc.target/sh/pr51244-6.c
Normal file
15
gcc/testsuite/gcc.target/sh/pr51244-6.c
Normal file
@ -0,0 +1,15 @@
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/* Check that no unnecessary sign or zero extension insn is generated after
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a negc or movrt insn that stores the inverted T bit in a reg. */
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/* { dg-do compile { target "sh*-*-*" } } */
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/* { dg-options "-O1" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */
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/* { dg-final { scan-assembler-not "extu|exts" } } */
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float
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test_00 (float q[4], float m[9])
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{
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float s0 = m[0] + m[1];
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float s1 = m[0] - m[1];
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return q[s0 > s1 ? 0 : 1];
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}
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