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pa.h (EXTRA_CONSTRAINT): Loosen conditions for match of 'Q' and 'T' while reload is running.
* pa.h (EXTRA_CONSTRAINT): Loosen conditions for match of
'Q' and 'T' while reload is running.
* pa/pa.c (hppa_legitimize_address): Rework to generate more
indexed and scaled indexed addressing.
* pa/pa.md (scaled indexed store): Add define_splits to undo
pessimizations created by hppa_legitimize_address for integer
stores.
From-SVN: r12892
This commit is contained in:
Jeff Law
parent
085540da9c
commit
78c0acfdd3
@ -771,11 +771,7 @@ hppa_legitimize_address (x, oldx, mode)
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return plus_constant (ptr_reg, offset - newoffset);
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}
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/* Try to arrange things so that indexing modes can be used, but
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only do so if indexing is safe.
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Indexing is safe when the second operand for the outer PLUS
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is a REG, SUBREG, SYMBOL_REF or the like. */
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/* Handle (plus (mult (a) (shadd_constant)) (b)). */
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if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
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&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
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@ -786,66 +782,145 @@ hppa_legitimize_address (x, oldx, mode)
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{
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int val = INTVAL (XEXP (XEXP (x, 0), 1));
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rtx reg1, reg2;
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reg1 = force_reg (Pmode, force_operand (XEXP (x, 1), 0));
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reg2 = force_reg (Pmode,
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force_operand (XEXP (XEXP (x, 0), 0), 0));
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return force_reg (Pmode,
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gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode, reg2,
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GEN_INT (val)),
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reg1));
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reg1 = XEXP (x, 1);
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if (GET_CODE (reg1) != REG)
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reg1 = force_reg (Pmode, force_operand (reg1, 0));
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reg2 = XEXP (XEXP (x, 0), 0);
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if (GET_CODE (reg2) != REG)
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reg2 = force_reg (Pmode, force_operand (reg2, 0));
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if (INTVAL (XEXP (XEXP (x, 0), 1)) != GET_MODE_SIZE (mode))
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{
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reg2 = force_reg (Pmode, gen_rtx (MULT, Pmode, reg2, GEN_INT (val)));
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return force_reg (Pmode, gen_rtx (PLUS, Pmode, reg1, reg2));
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}
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return force_reg (Pmode, gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode,
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reg2, GEN_INT (val)),
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reg1));
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}
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/* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
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Only do so for floating point modes since this is more speculative
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and we lose if it's an integer store. */
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if ((mode == DFmode || mode == SFmode)
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&& GET_CODE (x) == PLUS
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if (GET_CODE (x) == PLUS
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&& GET_CODE (XEXP (x, 0)) == PLUS
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&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
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&& GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
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&& shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))))
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&& shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
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&& (mode == SFmode || mode == DFmode))
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{
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rtx regx1, regx2;
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/* Add the two unscaled terms B and C; if either B or C isn't
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a register or small constant int, then fail. */
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regx1 = XEXP (XEXP (x, 0), 1);
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if (! (GET_CODE (regx1) == REG
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|| (GET_CODE (regx1) == CONST_INT
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&& INT_14_BITS (regx1))))
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/* First, try and figure out what to use as a base register. */
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rtx reg1, reg2, base, idx, orig_base;
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reg1 = XEXP (XEXP (x, 0), 1);
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reg2 = XEXP (x, 1);
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base = NULL_RTX;
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idx = NULL_RTX;
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/* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
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then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
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know it's a base register below. */
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if (GET_CODE (reg1) != REG)
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reg1 = force_reg (Pmode, force_operand (reg1, 0));
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if (GET_CODE (reg2) != REG)
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reg2 = force_reg (Pmode, force_operand (reg2, 0));
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/* Figure out what the base and index are. */
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if (GET_CODE (reg1) == REG
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&& REGNO_POINTER_FLAG (REGNO (reg1)))
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{
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base = reg1;
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orig_base = XEXP (XEXP (x, 0), 1);
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idx = gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode,
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XEXP (XEXP (XEXP (x, 0), 0), 0),
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XEXP (XEXP (XEXP (x, 0), 0), 1)),
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XEXP (x, 1));
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}
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else if (GET_CODE (reg2) == REG
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&& REGNO_POINTER_FLAG (REGNO (reg2)))
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{
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base = reg2;
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orig_base = XEXP (x, 1);
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idx = XEXP (x, 0);
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}
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if (base == 0)
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return orig;
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/* If the index adds a large constant, try to scale the
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constant so that it can be loaded with only one insn. */
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if (GET_CODE (XEXP (idx, 1)) == CONST_INT
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&& VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
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/ INTVAL (XEXP (XEXP (idx, 0), 1)))
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&& INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
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{
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/* Divide the CONST_INT by the scale factor, then add it to A. */
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int val = INTVAL (XEXP (idx, 1));
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val /= INTVAL (XEXP (XEXP (idx, 0), 1));
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reg1 = XEXP (XEXP (idx, 0), 0);
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if (GET_CODE (reg1) != REG)
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reg1 = force_reg (Pmode, force_operand (reg1, 0));
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reg1 = force_reg (Pmode, gen_rtx (PLUS, Pmode, reg1, GEN_INT (val)));
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/* We can now generate a simple scaled indexed address. */
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return force_reg (Pmode, gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode, reg1,
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XEXP (XEXP (idx, 0), 1)),
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base));
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}
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/* If B + C is still a valid base register, then add them. */
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if (GET_CODE (XEXP (idx, 1)) == CONST_INT
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&& INTVAL (XEXP (idx, 1)) <= 4096
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&& INTVAL (XEXP (idx, 1)) >= -4096)
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{
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int val = INTVAL (XEXP (XEXP (idx, 0), 1));
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rtx reg1, reg2;
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reg1 = force_reg (Pmode, gen_rtx (PLUS, Pmode, base, XEXP (idx, 1)));
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reg2 = XEXP (XEXP (idx, 0), 0);
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if (GET_CODE (reg2) != CONST_INT)
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reg2 = force_reg (Pmode, force_operand (reg2, 0));
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return force_reg (Pmode, gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode,
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reg2, GEN_INT (val)),
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reg1));
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}
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/* Get the index into a register, then add the base + index and
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return a register holding the result. */
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/* First get A into a register. */
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reg1 = XEXP (XEXP (idx, 0), 0);
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if (GET_CODE (reg1) != REG)
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reg1 = force_reg (Pmode, force_operand (reg1, 0));
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/* And get B into a register. */
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reg2 = XEXP (idx, 1);
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if (GET_CODE (reg2) != REG)
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reg2 = force_reg (Pmode, force_operand (reg2, 0));
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reg1 = force_reg (Pmode, gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode, reg1,
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XEXP (XEXP (idx, 0), 1)),
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reg2));
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/* Add the result to our base register and return. */
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return force_reg (Pmode, gen_rtx (PLUS, Pmode, base, reg1));
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regx2 = XEXP (x, 1);
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if (! (GET_CODE (regx2) == REG
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|| (GET_CODE (regx2) == CONST_INT
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&& INT_14_BITS (regx2))))
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return orig;
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/* Add them, make sure the result is in canonical form. */
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if (GET_CODE (regx1) == REG)
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regx1 = force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regx2));
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else if (GET_CODE (regx2) == REG)
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regx1 = force_reg (Pmode, gen_rtx (PLUS, Pmode, regx2, regx1));
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else
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regx1 = force_reg (Pmode, gen_rtx (PLUS, Pmode,
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force_reg (Pmode, regx1),
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regx2));
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/* Get the term to scale in a register. */
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regx2 = XEXP (XEXP (XEXP (x, 0), 0), 0);
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if (GET_CODE (regx2) != REG)
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regx2 = force_reg (Pmode, force_operand (regx2, 0));
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/* And make an indexed address. */
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regx2 = gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode, regx2,
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XEXP (XEXP (XEXP (x, 0), 0), 1)),
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regx1);
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/* Return it. */
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return force_reg (Pmode, regx2);
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}
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/* Uh-oh. We might have an address for x[n-100000]. This needs
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@ -879,12 +954,42 @@ hppa_legitimize_address (x, oldx, mode)
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(plus (mult (reg) (shadd_const))
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(const (plus (symbol_ref) (const_int))))
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Where const_int can be divided evenly by shadd_const and
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added to (reg). This allows more scaled indexed addresses. */
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if ((mode == DFmode || mode == SFmode)
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&& GET_CODE (XEXP (y, 0)) == SYMBOL_REF
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Where const_int is small. In that case the const
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expression is a valid pointer for indexing.
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If const_int is big, but can be divided evenly by shadd_const
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and added to (reg). This allows more scaled indexed addresses. */
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if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (x, 0)) == MULT
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&& GET_CODE (XEXP (y, 1)) == CONST_INT
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&& INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0)
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&& INTVAL (XEXP (y, 1)) >= -4096
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&& INTVAL (XEXP (y, 1)) <= 4095
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&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
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&& shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
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{
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int val = INTVAL (XEXP (XEXP (x, 0), 1));
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rtx reg1, reg2;
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reg1 = XEXP (x, 1);
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if (GET_CODE (reg1) != REG)
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reg1 = force_reg (Pmode, force_operand (reg1, 0));
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reg2 = XEXP (XEXP (x, 0), 0);
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if (GET_CODE (reg2) != REG)
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reg2 = force_reg (Pmode, force_operand (reg2, 0));
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return force_reg (Pmode, gen_rtx (PLUS, Pmode,
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gen_rtx (MULT, Pmode,
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reg2, GEN_INT (val)),
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reg1));
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}
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else if ((mode == DFmode || mode == SFmode)
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&& GET_CODE (XEXP (y, 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (x, 0)) == MULT
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&& GET_CODE (XEXP (y, 1)) == CONST_INT
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&& INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
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&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
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&& shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
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{
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regx1
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= force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
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@ -1405,7 +1405,8 @@ extern struct rtx_def *hppa_builtin_saveregs ();
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((C) == 'Q' ? \
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(IS_RELOADING_PSEUDO_P (OP) \
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|| (GET_CODE (OP) == MEM \
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&& memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
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&& (memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
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|| reload_in_progress) \
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&& ! symbolic_memory_operand (OP, VOIDmode) \
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&& !(GET_CODE (XEXP (OP, 0)) == PLUS \
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&& (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
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@ -1416,7 +1417,8 @@ extern struct rtx_def *hppa_builtin_saveregs ();
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&& (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT \
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|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT) \
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&& (move_operand (OP, GET_MODE (OP)) \
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|| memory_address_p (GET_MODE (OP), XEXP (OP, 0))))\
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|| memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
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|| reload_in_progress)) \
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: ((C) == 'T' ? \
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(GET_CODE (OP) == MEM \
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/* Using DFmode forces only short displacements \
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@ -1664,6 +1664,52 @@
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(set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
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"")
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;; hppa_legitimize_address goes to a great deal of trouble to
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;; create addresses which use indexing. In some cases, this
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;; is a lose because there isn't any store instructions which
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;; allow indexed addresses (with integer register source).
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;;
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;; These define_splits try to turn a 3 insn store into
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;; a 2 insn store with some creative RTL rewriting.
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(define_split
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[(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "shadd_operand" ""))
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(plus:SI (match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "const_int_operand" ""))))
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(match_operand:SI 4 "register_operand" ""))
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(clobber (match_operand:SI 5 "register_operand" ""))]
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""
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[(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
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(match_dup 2)))
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(set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
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"")
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(define_split
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[(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "shadd_operand" ""))
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(plus:SI (match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "const_int_operand" ""))))
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(match_operand:HI 4 "register_operand" ""))
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(clobber (match_operand:SI 5 "register_operand" ""))]
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""
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[(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
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(match_dup 2)))
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(set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
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"")
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(define_split
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[(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
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(match_operand:SI 1 "shadd_operand" ""))
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(plus:SI (match_operand:SI 2 "register_operand" "")
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(match_operand:SI 3 "const_int_operand" ""))))
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(match_operand:QI 4 "register_operand" ""))
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(clobber (match_operand:SI 5 "register_operand" ""))]
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""
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[(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
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(match_dup 2)))
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(set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
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"")
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand" "")
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(match_operand:HI 1 "general_operand" ""))]
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