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genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode.
* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a MODE_PARTIAL_INT mode. * config/bfin/bfin-modes.def: Add V2PDI and V2SI. * config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers for CONST_INTs. (hard_regno_mode_ok): V2PDImode is ok for accumulators. * config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle V2PDImode. * config/bfin/predicates.md (const01_operand, vec_shift_operand): New predicates. * config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG): New constants. (MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS, MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2, MACFLAG_IH): Likewise. (movstricthi_1): Renamed from "*movstricthi". (load_accumulator, load_accumulator_pair, movsi_insv, insv, ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3, abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high, movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low, movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low, movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3, addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3, sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3, addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3, mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2, ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi, flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly, flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts, flag_macv2hi_parts, flag_macv2hi_parts_acconly, flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns. From-SVN: r113245
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
ec23e15b4c
commit
75d8b2d014
@ -1,3 +1,37 @@
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2006-04-25 Bernd Schmidt <bernd.schmidt@analog.com>
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* genmodes.c (make_vector_mode): Allow making VECTOR_MODE_INT of a
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MODE_PARTIAL_INT mode.
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* config/bfin/bfin-modes.def: Add V2PDI and V2SI.
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* config/bfin/bfin.c (print_operand): Add macflag and mac/msu modifiers
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for CONST_INTs.
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(hard_regno_mode_ok): V2PDImode is ok for accumulators.
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* config/bfin/bfin.h (CLASS_MAX_NREGS, HARD_REGNO_NREGS): Handle
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V2PDImode.
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* config/bfin/predicates.md (const01_operand, vec_shift_operand):
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New predicates.
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* config/bfin/bfin.md (UNSPEC_MUL_WITH_FLAG, UNSPEC_MAC_WITH_FLAG):
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New constants.
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(MACFLAG_NONE, MACFLAG_T, MACFLAG_FU, MACFLAG_TFU, MACFLAG_IS,
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MACFLAG_IU, MACFLAG_W32, MACFLAG_M, MACFLAG_S2RND, MACFLAG_ISS2,
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MACFLAG_IH): Likewise.
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(movstricthi_1): Renamed from "*movstricthi".
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(load_accumulator, load_accumulator_pair, movsi_insv, insv,
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ssaddsi3, sssubsi3, ssnegsi2, signbitssi2, smaxhi3, sminhi3,
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abshi2, neghi2, ssneghi2, signbitshi2, movhi_low2high,
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movhi_high2high, movhi_low2low, movhi_high2low, movhiv2hi_low,
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movhiv2hi_high, composev2hi, movv2hi_hi, movv2hi_hi_low,
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movv2hi_hi_high, ssaddhi3, sssubhi3, ssaddv2hi3, sssubv2hi3,
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addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3,
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sublohiv2hi3, subhilov2hi3, sssublohiv2hi3, sssubhilov2hi3,
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addlohiv2hi3, addhilov2hi3, ssaddlohiv2hi3, ssaddhilov2hi3,
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mulhisi_ll, mulhisi_lh, mulhisi_hl, mulhisi_hh, ssnegv2hi2,
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ssashiftv2hi3, ssashifthi3, lshiftv2hi3, lshifthi3, packv2hi,
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flag_mulhi, flag_mulhisi_parts, flag_machi, flag_machi_acconly,
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flag_macinithi, flag_macinit1hi, flag_mulv2hi, flag_mulv2hi_parts,
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flag_macv2hi_parts, flag_macv2hi_parts_acconly,
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flag_macinitv2hi_parts, flag_macinit1v2hi_parts): New patterns.
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2006-04-24 Geoffrey Keating <geoffk@apple.com>
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* dwarf2out.c (verify_marks_clear): New.
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@ -22,4 +22,8 @@
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/* PDImode for the 40 bit accumulators. */
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PARTIAL_INT_MODE (DI);
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/* Two of those - covering both accumulators for vector multiplications. */
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VECTOR_MODE (INT, PDI, 2);
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VECTOR_MODE (INT, HI, 2); /* V2HI */
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VECTOR_MODE (INT, SI, 2); /* V2SI - occasionally used. */
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@ -1259,9 +1259,60 @@ print_operand (FILE *file, rtx x, char code)
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break;
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case CONST_INT:
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if (code == 'M')
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{
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switch (INTVAL (x))
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{
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case MACFLAG_NONE:
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break;
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case MACFLAG_FU:
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fputs ("(FU)", file);
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break;
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case MACFLAG_T:
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fputs ("(T)", file);
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break;
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case MACFLAG_TFU:
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fputs ("(TFU)", file);
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break;
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case MACFLAG_W32:
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fputs ("(W32)", file);
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break;
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case MACFLAG_IS:
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fputs ("(IS)", file);
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break;
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case MACFLAG_IU:
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fputs ("(IU)", file);
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break;
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case MACFLAG_IH:
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fputs ("(IH)", file);
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break;
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case MACFLAG_M:
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fputs ("(M)", file);
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break;
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case MACFLAG_ISS2:
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fputs ("(ISS2)", file);
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break;
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case MACFLAG_S2RND:
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fputs ("(S2RND)", file);
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break;
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default:
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gcc_unreachable ();
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}
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break;
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}
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else if (code == 'b')
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{
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if (INTVAL (x) == 0)
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fputs ("+=", file);
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else if (INTVAL (x) == 1)
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fputs ("-=", file);
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else
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gcc_unreachable ();
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break;
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}
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/* Moves to half registers with d or h modifiers always use unsigned
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constants. */
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if (code == 'd')
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else if (code == 'd')
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x = GEN_INT ((INTVAL (x) >> 16) & 0xffff);
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else if (code == 'h')
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x = GEN_INT (INTVAL (x) & 0xffff);
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@ -1672,7 +1723,7 @@ hard_regno_mode_ok (int regno, enum machine_mode mode)
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return D_REGNO_P (regno);
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if (class == CCREGS)
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return mode == BImode;
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if (mode == PDImode)
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if (mode == PDImode || mode == V2PDImode)
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return regno == REG_A0 || regno == REG_A1;
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if (mode == SImode
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&& TEST_HARD_REG_BIT (reg_class_contents[PROLOGUE_REGS], regno))
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@ -509,12 +509,14 @@ enum reg_class
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/* Return the maximum number of consecutive registers
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needed to represent mode MODE in a register of class CLASS. */
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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#define CLASS_MAX_NREGS(CLASS, MODE) \
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((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
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: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
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#define HARD_REGNO_NREGS(REGNO, MODE) \
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((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) \
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? 1 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
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((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
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: (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
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: CLASS_MAX_NREGS (GENERAL_REGS, MODE))
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/* A C expression that is nonzero if hard register TO can be
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considered for use as a rename register for FROM register */
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File diff suppressed because it is too large
Load Diff
@ -56,6 +56,14 @@
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(ior (match_operand 0 "register_operand")
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(match_code "const_int")))
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(define_predicate "const01_operand"
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(match_test "op == const0_rtx || op == const1_rtx"))
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(define_predicate "vec_shift_operand"
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(ior (and (match_code "const_int")
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(match_test "INTVAL (op) >= -16 && INTVAL (op) < 15"))
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(match_operand 0 "register_operand")))
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;; Like register_operand, but make sure that hard regs have a valid mode.
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(define_predicate "valid_reg_operand"
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(match_operand 0 "register_operand")
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@ -635,7 +635,9 @@ make_vector_mode (enum mode_class bclass,
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error ("%s:%d: no mode \"%s\"", file, line, base);
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return;
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}
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if (component->cl != bclass)
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if (component->cl != bclass
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&& (component->cl != MODE_PARTIAL_INT
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|| bclass != MODE_INT))
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{
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error ("%s:%d: mode \"%s\" is not class %s",
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file, line, base, mode_class_names[bclass] + 5);
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