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[AArch64] Add support for SVE F{MAX,MIN}NM immediate
This patch uses the immediate forms of FMAXNM and FMINNM for unconditional arithmetic. The same rules apply to FMAX and FMIN, but we only generate those via the ACLE. 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/predicates.md (aarch64_sve_float_maxmin_immediate) (aarch64_sve_float_maxmin_operand): New predicates. * config/aarch64/constraints.md (vsB): New constraint. (vsM): Fix typo. * config/aarch64/iterators.md (sve_pred_fp_rhs2_operand): Use aarch64_sve_float_maxmin_operand for UNSPEC_COND_FMAXNM and UNSPEC_COND_FMINNM. * config/aarch64/aarch64-sve.md (<maxmin_uns><SVE_F:mode>3): Use aarch64_sve_float_maxmin_operand for operand 2. (*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Likewise. Add alternatives for the constant forms. gcc/testsuite/ * gcc.target/aarch64/sve/fmaxnm_1.c: New test. * gcc.target/aarch64/sve/fminnm_1.c: Likewise. From-SVN: r274440
This commit is contained in:
Richard Sandiford
Richard Sandiford
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f8c22a8bba
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75079ddf9c
@ -1,3 +1,17 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/predicates.md (aarch64_sve_float_maxmin_immediate)
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(aarch64_sve_float_maxmin_operand): New predicates.
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* config/aarch64/constraints.md (vsB): New constraint.
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(vsM): Fix typo.
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* config/aarch64/iterators.md (sve_pred_fp_rhs2_operand): Use
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aarch64_sve_float_maxmin_operand for UNSPEC_COND_FMAXNM and
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UNSPEC_COND_FMINNM.
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* config/aarch64/aarch64-sve.md (<maxmin_uns><SVE_F:mode>3):
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Use aarch64_sve_float_maxmin_operand for operand 2.
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(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Likewise.
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Add alternatives for the constant forms.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/constraints.md (vsb): New constraint.
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@ -2604,7 +2604,7 @@
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[(match_dup 3)
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(const_int SVE_RELAXED_GP)
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(match_operand:SVE_F 1 "register_operand")
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(match_operand:SVE_F 2 "register_operand")]
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(match_operand:SVE_F 2 "aarch64_sve_float_maxmin_operand")]
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SVE_COND_FP_MAXMIN_PUBLIC))]
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"TARGET_SVE"
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{
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@ -2614,18 +2614,20 @@
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;; Predicated floating-point maximum/minimum.
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(define_insn "*<optab><mode>3"
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[(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
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[(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w, ?&w")
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(unspec:SVE_F
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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(match_operand:SI 4 "aarch64_sve_gp_strictness")
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(match_operand:SVE_F 2 "register_operand" "%0, w")
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(match_operand:SVE_F 3 "register_operand" "w, w")]
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(match_operand:SVE_F 2 "register_operand" "%0, 0, w, w")
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(match_operand:SVE_F 3 "aarch64_sve_float_maxmin_operand" "vsB, w, vsB, w")]
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SVE_COND_FP_MAXMIN_PUBLIC))]
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"TARGET_SVE"
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"@
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<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
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<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, #%3
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movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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[(set_attr "movprfx" "*,yes")]
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[(set_attr "movprfx" "*,*,yes,yes")]
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)
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;; Merging forms are handled through SVE_COND_FP_BINARY.
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@ -436,9 +436,16 @@
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and FSUB operations."
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(match_operand 0 "aarch64_sve_float_arith_immediate"))
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;; "B" for "bound".
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(define_constraint "vsB"
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"@internal
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A constraint that matches an immediate operand valid for SVE FMAX
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and FMIN operations."
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(match_operand 0 "aarch64_sve_float_maxmin_immediate"))
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(define_constraint "vsM"
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"@internal
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A constraint that matches an imediate operand valid for SVE FMUL
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A constraint that matches an immediate operand valid for SVE FMUL
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operations."
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(match_operand 0 "aarch64_sve_float_mul_immediate"))
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@ -2075,7 +2075,7 @@
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(define_int_attr sve_pred_fp_rhs2_operand
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[(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
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(UNSPEC_COND_FDIV "register_operand")
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(UNSPEC_COND_FMAXNM "register_operand")
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(UNSPEC_COND_FMINNM "register_operand")
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(UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand")
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(UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand")
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(UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
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(UNSPEC_COND_FSUB "register_operand")])
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@ -655,6 +655,11 @@
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(and (match_code "const,const_vector")
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(match_test "aarch64_sve_float_mul_immediate_p (op)")))
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(define_predicate "aarch64_sve_float_maxmin_immediate"
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(and (match_code "const_vector")
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(ior (match_test "op == CONST0_RTX (GET_MODE (op))")
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(match_test "op == CONST1_RTX (GET_MODE (op))"))))
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(define_predicate "aarch64_sve_arith_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_sve_arith_immediate")))
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@ -708,6 +713,10 @@
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_sve_float_mul_immediate")))
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(define_predicate "aarch64_sve_float_maxmin_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_sve_float_maxmin_immediate")))
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(define_predicate "aarch64_sve_vec_perm_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_constant_vector_operand")))
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@ -1,3 +1,8 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/fmaxnm_1.c: New test.
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* gcc.target/aarch64/sve/fminnm_1.c: Likewise.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/smax_1.c: New test.
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45
gcc/testsuite/gcc.target/aarch64/sve/fmaxnm_1.c
Normal file
45
gcc/testsuite/gcc.target/aarch64/sve/fmaxnm_1.c
Normal file
@ -0,0 +1,45 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#ifndef FN
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#define FN(X) __builtin_fmax##X
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#endif
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#define DEF_LOOP(FN, TYPE, NAME, CONST) \
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void __attribute__ ((noipa)) \
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test_##TYPE##_##NAME (TYPE *__restrict x, \
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TYPE *__restrict y, int n) \
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{ \
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for (int i = 0; i < n; ++i) \
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x[i] = FN (y[i], CONST); \
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}
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#define TEST_TYPE(T, FN, TYPE) \
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T (FN, TYPE, zero, 0) \
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T (FN, TYPE, one, 1) \
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T (FN, TYPE, two, 2)
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#define TEST_ALL(T) \
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TEST_TYPE (T, FN (f16), _Float16) \
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TEST_TYPE (T, FN (f32), float) \
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TEST_TYPE (T, FN (f64), double)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
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21
gcc/testsuite/gcc.target/aarch64/sve/fminnm_1.c
Normal file
21
gcc/testsuite/gcc.target/aarch64/sve/fminnm_1.c
Normal file
@ -0,0 +1,21 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#define FN(X) __builtin_fmin##X
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#include "fmaxnm_1.c"
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #0\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, #1\.0\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.h, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.s, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfmov\tz[0-9]+\.d, #2\.0} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 1 } } */
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