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re PR target/42165 (-masm=intel doesn't know how to print AVX instructions)
PR target/42165 * config/i386/i386.c (print_operand): For 32-byte memory use YMMWORD in -masm=intel mode. Use TBYTE instead of XWORD. * config/i386/i386.md (crc32modesuffix): Expand to nothing in -masm=intel mode. (sse4_2_crc32di): Print just crc32 instead of crc32q in -masm=intel mode. * config/i386/mmx.md (*mmx_pinsrw): Print correct size of memory operand in -masm=intel mode. * config/i386/sse.md (*avx_pinsr<ssevecsize>, *sse4_1_pinsrb, *sse2_pinsrw): Likewise. (sse_cvtss2siq, sse_cvtss2siq_2, sse_cvttss2siq): Don't print q suffix in -masm=intel mode. From-SVN: r154652
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
8a2bbeef66
commit
72b2bc46f5
@ -3,6 +3,20 @@
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* print-rtl.c (print_rtx): When printing newline, append
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print_rtx_head and indentation after the newline.
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PR target/42165
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* config/i386/i386.c (print_operand): For 32-byte memory use
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YMMWORD in -masm=intel mode. Use TBYTE instead of XWORD.
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* config/i386/i386.md (crc32modesuffix): Expand to nothing
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in -masm=intel mode.
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(sse4_2_crc32di): Print just crc32 instead of crc32q in
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-masm=intel mode.
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* config/i386/mmx.md (*mmx_pinsrw): Print correct size of
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memory operand in -masm=intel mode.
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* config/i386/sse.md (*avx_pinsr<ssevecsize>, *sse4_1_pinsrb,
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*sse2_pinsrw): Likewise.
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(sse_cvtss2siq, sse_cvtss2siq_2, sse_cvttss2siq): Don't print
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q suffix in -masm=intel mode.
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2009-11-25 Eric Botcazou <ebotcazou@adacore.com>
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PR target/10127
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@ -11842,13 +11842,14 @@ print_operand (FILE *file, rtx x, int code)
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case 2: size = "WORD"; break;
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case 4: size = "DWORD"; break;
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case 8: size = "QWORD"; break;
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case 12: size = "XWORD"; break;
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case 12: size = "TBYTE"; break;
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case 16:
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if (GET_MODE (x) == XFmode)
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size = "XWORD";
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size = "TBYTE";
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else
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size = "XMMWORD";
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break;
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case 32: size = "YMMWORD"; break;
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default:
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gcc_unreachable ();
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}
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@ -21168,7 +21168,7 @@
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[(set_attr "type" "multi")])
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(define_mode_iterator CRC32MODE [QI HI SI])
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(define_mode_attr crc32modesuffix [(QI "b") (HI "w") (SI "l")])
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(define_mode_attr crc32modesuffix [(QI "{b}") (HI "{w}") (SI "{l}")])
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(define_mode_attr crc32modeconstraint [(QI "qm") (HI "rm") (SI "rm")])
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(define_insn "sse4_2_crc32<mode>"
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@ -21199,7 +21199,7 @@
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(match_operand:DI 2 "nonimmediate_operand" "rm")]
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UNSPEC_CRC32))]
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"TARGET_64BIT && (TARGET_SSE4_2 || TARGET_CRC32)"
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"crc32q\t{%2, %0|%0, %2}"
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"crc32{q}\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog1")
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(set_attr "prefix_rep" "1")
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(set_attr "prefix_extra" "1")
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@ -1250,7 +1250,10 @@
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"TARGET_SSE || TARGET_3DNOW_A"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
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if (MEM_P (operands[2]))
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return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
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else
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return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
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}
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[(set_attr "type" "mmxcvt")
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(set_attr "length_immediate" "1")
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@ -2734,7 +2734,7 @@
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(parallel [(const_int 0)]))]
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UNSPEC_FIX_NOTRUNC))]
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"TARGET_SSE && TARGET_64BIT"
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"%vcvtss2siq\t{%1, %0|%0, %1}"
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"%vcvtss2si{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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(set_attr "athlon_decode" "double,vector")
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(set_attr "prefix_rep" "1")
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@ -2746,7 +2746,7 @@
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(unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
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UNSPEC_FIX_NOTRUNC))]
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"TARGET_SSE && TARGET_64BIT"
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"%vcvtss2siq\t{%1, %0|%0, %1}"
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"%vcvtss2si{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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(set_attr "athlon_decode" "double,vector")
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(set_attr "amdfam10_decode" "double,double")
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@ -2776,7 +2776,7 @@
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(match_operand:V4SF 1 "nonimmediate_operand" "x,m")
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(parallel [(const_int 0)]))))]
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"TARGET_SSE && TARGET_64BIT"
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"%vcvttss2siq\t{%1, %0|%0, %1}"
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"%vcvttss2si{q}\t{%1, %0|%0, %1}"
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[(set_attr "type" "sseicvt")
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(set_attr "athlon_decode" "double,vector")
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(set_attr "amdfam10_decode" "double,double")
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@ -7127,7 +7127,10 @@
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"TARGET_AVX"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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if (MEM_P (operands[2]))
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return "vpinsr<ssevecsize>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
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else
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return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
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}
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[(set_attr "type" "sselog")
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(set (attr "prefix_extra")
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@ -7148,7 +7151,10 @@
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"TARGET_SSE4_1"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
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if (MEM_P (operands[2]))
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return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
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else
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return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
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}
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[(set_attr "type" "sselog")
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(set_attr "prefix_extra" "1")
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@ -7165,7 +7171,10 @@
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"TARGET_SSE2"
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{
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operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
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return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
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if (MEM_P (operands[2]))
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return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
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else
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return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
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}
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[(set_attr "type" "sselog")
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(set_attr "prefix_data16" "1")
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