mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-04-03 08:50:31 +08:00
Code Issues Packages Projects Releases Wiki Activity

gcc, Arm: Revert changes to {get,set}_fpscr

Browse Source 
MVE made changes to {get,set}_fpscr to enable the compiler to optimize
unneccesary gets and sets when using these for intrinsics that use and/or write
the carry bit.  However, these actually get and set the full FPSCR register and
are used by fp env intrinsics to modify the fp context.  So MVE should not be
using these.

gcc/ChangeLog:
2020-03-20  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
	(VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
	* config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
This commit is contained in:
Andre Simoes Dias Vieira 2020-03-20 09:18:18 +00:00 committed by Andre Vieira
parent 005f6fc59e
commit 719c864225
3 changed files with 10 additions and 5 deletions

6
gcc/ChangeLog

@ -1,3 +1,9 @@
2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/unspecs.md (UNSPEC_GET_FPSCR): Rename this to ...
(VUNSPEC_GET_FPSCR): ... this, and move it to vunspec.
* config/arm/vfp.md: (get_fpscr, set_fpscr): Revert to old patterns.
2020-03-20 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/mve.md (mve_mov<mode>): Fix R->R case.

2
gcc/config/arm/unspecs.md

@ -170,7 +170,6 @@
UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction.
UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
UNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.
])
@ -217,6 +216,7 @@
VUNSPEC_SLX ; Represent a store-register-release-exclusive.
VUNSPEC_LDA ; Represent a store-register-acquire.
VUNSPEC_STL ; Represent a store-register-release.
VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.
VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content.
VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
VUNSPEC_CDP ; Represent the coprocessor cdp instruction.

7
gcc/config/arm/vfp.md

@ -2096,9 +2096,8 @@
;; Write Floating-point Status and Control Register.
(define_insn "set_fpscr"
[(set (reg:SI VFPCC_REGNUM)
(unspec_volatile:SI
[(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR))]
[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
VUNSPEC_SET_FPSCR)]
"TARGET_VFP_BASE"
"mcr\\tp10, 7, %0, cr1, cr0, 0\\t @SET_FPSCR"
[(set_attr "type" "mrs")])
@ -2106,7 +2105,7 @@
;; Read Floating-point Status and Control Register.
(define_insn "get_fpscr"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR))]
(unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FPSCR))]
"TARGET_VFP_BASE"
"mrc\\tp10, 7, %0, cr1, cr0, 0\\t @GET_FPSCR"
[(set_attr "type" "mrs")])