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rs6000: Move various non-vector things out of altivec.md
* config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32, UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to... * config/rs6000/rs6000.md (unspec): ... here. * config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb, *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, cmpeqb, *cmpeqb_internal): Delete, move to... * config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb, *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, cmpeqb, *cmpeqb_internal): ... here. From-SVN: r274834
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
db376f458e
commit
71278ecd4e
@ -1,3 +1,15 @@
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2019-08-22 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32,
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UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to...
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* config/rs6000/rs6000.md (unspec): ... here.
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* config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb,
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*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
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cmpeqb, *cmpeqb_internal): Delete, move to...
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* config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb,
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*cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal,
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cmpeqb, *cmpeqb_internal): ... here.
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2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm_acle.h: Use arch=armv8-a+crc+simd pragma for CRC32
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@ -80,9 +80,6 @@
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UNSPEC_VUPKHPX
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UNSPEC_VUPKLPX
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UNSPEC_CONVERT_4F32_8I16
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UNSPEC_DARN
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UNSPEC_DARN_32
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UNSPEC_DARN_RAW
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UNSPEC_DST
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UNSPEC_DSTT
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UNSPEC_DSTST
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@ -161,9 +158,6 @@
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UNSPEC_BCDADD
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UNSPEC_BCDSUB
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UNSPEC_BCD_OVERFLOW
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UNSPEC_CMPRB
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UNSPEC_CMPRB2
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UNSPEC_CMPEQB
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UNSPEC_VRLMI
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UNSPEC_VRLNM
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])
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@ -4107,223 +4101,6 @@
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"bcd<bcd_add_sub>. %0,%1,%2,%3"
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[(set_attr "type" "vecsimple")])
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(define_insn "darn_32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
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"TARGET_P9_MISC"
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"darn %0,0"
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[(set_attr "type" "integer")])
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(define_insn "darn_raw"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
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"TARGET_P9_MISC && TARGET_64BIT"
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"darn %0,2"
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[(set_attr "type" "integer")])
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(define_insn "darn"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_DARN))]
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"TARGET_P9_MISC && TARGET_64BIT"
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"darn %0,1"
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[(set_attr "type" "integer")])
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;; Test byte within range.
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;;
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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;; represents a byte whose value is ignored in this context and
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;; vv, the least significant byte, holds the byte value that is to
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;; be tested for membership within the range specified by operand 2.
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;; The bytes of operand 2 are organized as xx:xx:hi:lo.
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;;
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;; Return in target register operand 0 a value of 1 if lo <= vv and
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;; vv <= hi. Otherwise, set register operand 0 to 0.
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;;
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;; Though the instructions to which this expansion maps operate on
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;; 64-bit registers, the current implementation only operates on
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;; SI-mode operands as the high-order bits provide no information
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;; that is not already available in the low-order bits. To avoid the
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;; costs of data widening operations, future enhancements might allow
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;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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(define_expand "cmprb"
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[(set (match_dup 3)
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPRB))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(if_then_else:SI (lt (match_dup 3)
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(const_int 0))
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(const_int -1)
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(if_then_else (gt (match_dup 3)
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(const_int 0))
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(const_int 1)
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(const_int 0))))]
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"TARGET_P9_MISC"
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{
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operands[3] = gen_reg_rtx (CCmode);
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})
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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;; represents a byte whose value is ignored in this context and
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;; vv, the least significant byte, holds the byte value that is to
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;; be tested for membership within the range specified by operand 2.
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;; The bytes of operand 2 are organized as xx:xx:hi:lo.
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;;
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;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
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;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
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;; 3 bits of the target CR register are all set to 0.
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(define_insn "*cmprb_internal"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPRB))]
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"TARGET_P9_MISC"
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"cmprb %0,0,%1,%2"
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[(set_attr "type" "logical")])
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;; Set operand 0 register to -1 if the LT bit (0x8) of condition
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;; register operand 1 is on. Otherwise, set operand 0 register to 1
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;; if the GT bit (0x4) of condition register operand 1 is on.
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;; Otherwise, set operand 0 to 0. Note that the result stored into
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;; register operand 0 is non-zero iff either the LT or GT bits are on
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;; within condition register operand 1.
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(define_insn "setb_signed"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
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(const_int 0))
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(const_int -1)
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(if_then_else (gt (match_dup 1)
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(const_int 0))
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(const_int 1)
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(const_int 0))))]
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"TARGET_P9_MISC"
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"setb %0,%1"
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[(set_attr "type" "logical")])
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(define_insn "setb_unsigned"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
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(const_int 0))
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(const_int -1)
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(if_then_else (gtu (match_dup 1)
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(const_int 0))
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(const_int 1)
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(const_int 0))))]
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"TARGET_P9_MISC"
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"setb %0,%1"
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[(set_attr "type" "logical")])
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;; Test byte within two ranges.
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;;
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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;; represents a byte whose value is ignored in this context and
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;; vv, the least significant byte, holds the byte value that is to
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;; be tested for membership within the range specified by operand 2.
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;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
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;;
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;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
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;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
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;; operand 0 to 0.
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;;
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;; Though the instructions to which this expansion maps operate on
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;; 64-bit registers, the current implementation only operates on
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;; SI-mode operands as the high-order bits provide no information
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;; that is not already available in the low-order bits. To avoid the
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;; costs of data widening operations, future enhancements might allow
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;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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(define_expand "cmprb2"
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[(set (match_dup 3)
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPRB2))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(if_then_else:SI (lt (match_dup 3)
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(const_int 0))
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(const_int -1)
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(if_then_else (gt (match_dup 3)
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(const_int 0))
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(const_int 1)
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(const_int 0))))]
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"TARGET_P9_MISC"
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{
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operands[3] = gen_reg_rtx (CCmode);
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})
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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;; represents a byte whose value is ignored in this context and
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;; vv, the least significant byte, holds the byte value that is to
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;; be tested for membership within the ranges specified by operand 2.
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;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
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;;
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;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
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;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
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;; Otherwise, set the GT bit to 0. The other 3 bits of the target
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;; CR register are all set to 0.
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(define_insn "*cmprb2_internal"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPRB2))]
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"TARGET_P9_MISC"
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"cmprb %0,1,%1,%2"
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[(set_attr "type" "logical")])
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;; Test byte membership within set of 8 bytes.
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;;
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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;; represents a byte whose value is ignored in this context and
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;; vv, the least significant byte, holds the byte value that is to
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;; be tested for membership within the set specified by operand 2.
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;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
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;;
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;; Return in target register operand 0 a value of 1 if vv equals one
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;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
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;; register operand 0 to 0. Note that the 8 byte values held within
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;; operand 2 need not be unique.
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;;
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;; Though the instructions to which this expansion maps operate on
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;; 64-bit registers, the current implementation requires that operands
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;; 0 and 1 have mode SI as the high-order bits provide no information
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;; that is not already available in the low-order bits. To avoid the
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;; costs of data widening operations, future enhancements might allow
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;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
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(define_expand "cmpeqb"
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[(set (match_dup 3)
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:DI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPEQB))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(if_then_else:SI (lt (match_dup 3)
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(const_int 0))
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(const_int -1)
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(if_then_else (gt (match_dup 3)
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(const_int 0))
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(const_int 1)
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(const_int 0))))]
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"TARGET_P9_MISC && TARGET_64BIT"
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{
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operands[3] = gen_reg_rtx (CCmode);
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})
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
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;; represents a byte whose value is ignored in this context and
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;; vv, the least significant byte, holds the byte value that is to
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;; be tested for membership within the set specified by operand 2.
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;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
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;;
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;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
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;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
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;; set the GT bit to zero. The other 3 bits of the target CR register
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;; are all set to 0.
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(define_insn "*cmpeqb_internal"
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:DI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPEQB))]
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"TARGET_P9_MISC && TARGET_64BIT"
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"cmpeqb %0,%1,%2"
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[(set_attr "type" "logical")])
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(define_expand "bcd<bcd_add_sub>_<code>"
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[(parallel [(set (reg:CCFP CR6_REGNO)
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(compare:CCFP
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@ -134,6 +134,12 @@
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UNSPEC_LSQ
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UNSPEC_FUSION_GPR
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UNSPEC_STACK_CHECK
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UNSPEC_DARN
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UNSPEC_DARN_32
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UNSPEC_DARN_RAW
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UNSPEC_CMPRB
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UNSPEC_CMPRB2
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UNSPEC_CMPEQB
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UNSPEC_ADD_ROUND_TO_ODD
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UNSPEC_SUB_ROUND_TO_ODD
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UNSPEC_MUL_ROUND_TO_ODD
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@ -14376,7 +14382,225 @@
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"xscmpuqp %0,%1,%2"
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[(set_attr "type" "veccmp")
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(set_attr "size" "128")])
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;; Miscellaneous ISA 3.0 (power9) instructions
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(define_insn "darn_32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(const_int 0)] UNSPEC_DARN_32))]
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"TARGET_P9_MISC"
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"darn %0,0"
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[(set_attr "type" "integer")])
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(define_insn "darn_raw"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))]
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"TARGET_P9_MISC && TARGET_64BIT"
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"darn %0,2"
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[(set_attr "type" "integer")])
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(define_insn "darn"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_DARN))]
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"TARGET_P9_MISC && TARGET_64BIT"
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"darn %0,1"
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[(set_attr "type" "integer")])
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;; Test byte within range.
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;;
|
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
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;; represents a byte whose value is ignored in this context and
|
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;; vv, the least significant byte, holds the byte value that is to
|
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;; be tested for membership within the range specified by operand 2.
|
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;; The bytes of operand 2 are organized as xx:xx:hi:lo.
|
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;;
|
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;; Return in target register operand 0 a value of 1 if lo <= vv and
|
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;; vv <= hi. Otherwise, set register operand 0 to 0.
|
||||
;;
|
||||
;; Though the instructions to which this expansion maps operate on
|
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;; 64-bit registers, the current implementation only operates on
|
||||
;; SI-mode operands as the high-order bits provide no information
|
||||
;; that is not already available in the low-order bits. To avoid the
|
||||
;; costs of data widening operations, future enhancements might allow
|
||||
;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
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(define_expand "cmprb"
|
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[(set (match_dup 3)
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
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UNSPEC_CMPRB))
|
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(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(if_then_else:SI (lt (match_dup 3)
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(const_int 0))
|
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(const_int -1)
|
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(if_then_else (gt (match_dup 3)
|
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(const_int 0))
|
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(const_int 1)
|
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(const_int 0))))]
|
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"TARGET_P9_MISC"
|
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{
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operands[3] = gen_reg_rtx (CCmode);
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})
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|
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;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
;; represents a byte whose value is ignored in this context and
|
||||
;; vv, the least significant byte, holds the byte value that is to
|
||||
;; be tested for membership within the range specified by operand 2.
|
||||
;; The bytes of operand 2 are organized as xx:xx:hi:lo.
|
||||
;;
|
||||
;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
|
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;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other
|
||||
;; 3 bits of the target CR register are all set to 0.
|
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(define_insn "*cmprb_internal"
|
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[(set (match_operand:CC 0 "cc_reg_operand" "=y")
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(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "gpc_reg_operand" "r")]
|
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UNSPEC_CMPRB))]
|
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"TARGET_P9_MISC"
|
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"cmprb %0,0,%1,%2"
|
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[(set_attr "type" "logical")])
|
||||
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;; Set operand 0 register to -1 if the LT bit (0x8) of condition
|
||||
;; register operand 1 is on. Otherwise, set operand 0 register to 1
|
||||
;; if the GT bit (0x4) of condition register operand 1 is on.
|
||||
;; Otherwise, set operand 0 to 0. Note that the result stored into
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||||
;; register operand 0 is non-zero iff either the LT or GT bits are on
|
||||
;; within condition register operand 1.
|
||||
(define_insn "setb_signed"
|
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y")
|
||||
(const_int 0))
|
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(const_int -1)
|
||||
(if_then_else (gt (match_dup 1)
|
||||
(const_int 0))
|
||||
(const_int 1)
|
||||
(const_int 0))))]
|
||||
"TARGET_P9_MISC"
|
||||
"setb %0,%1"
|
||||
[(set_attr "type" "logical")])
|
||||
|
||||
(define_insn "setb_unsigned"
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y")
|
||||
(const_int 0))
|
||||
(const_int -1)
|
||||
(if_then_else (gtu (match_dup 1)
|
||||
(const_int 0))
|
||||
(const_int 1)
|
||||
(const_int 0))))]
|
||||
"TARGET_P9_MISC"
|
||||
"setb %0,%1"
|
||||
[(set_attr "type" "logical")])
|
||||
|
||||
;; Test byte within two ranges.
|
||||
;;
|
||||
;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
;; represents a byte whose value is ignored in this context and
|
||||
;; vv, the least significant byte, holds the byte value that is to
|
||||
;; be tested for membership within the range specified by operand 2.
|
||||
;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
|
||||
;;
|
||||
;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and
|
||||
;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
|
||||
;; operand 0 to 0.
|
||||
;;
|
||||
;; Though the instructions to which this expansion maps operate on
|
||||
;; 64-bit registers, the current implementation only operates on
|
||||
;; SI-mode operands as the high-order bits provide no information
|
||||
;; that is not already available in the low-order bits. To avoid the
|
||||
;; costs of data widening operations, future enhancements might allow
|
||||
;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||
(define_expand "cmprb2"
|
||||
[(set (match_dup 3)
|
||||
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||
UNSPEC_CMPRB2))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(if_then_else:SI (lt (match_dup 3)
|
||||
(const_int 0))
|
||||
(const_int -1)
|
||||
(if_then_else (gt (match_dup 3)
|
||||
(const_int 0))
|
||||
(const_int 1)
|
||||
(const_int 0))))]
|
||||
"TARGET_P9_MISC"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (CCmode);
|
||||
})
|
||||
|
||||
;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
;; represents a byte whose value is ignored in this context and
|
||||
;; vv, the least significant byte, holds the byte value that is to
|
||||
;; be tested for membership within the ranges specified by operand 2.
|
||||
;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2.
|
||||
;;
|
||||
;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if
|
||||
;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
|
||||
;; Otherwise, set the GT bit to 0. The other 3 bits of the target
|
||||
;; CR register are all set to 0.
|
||||
(define_insn "*cmprb2_internal"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r")]
|
||||
UNSPEC_CMPRB2))]
|
||||
"TARGET_P9_MISC"
|
||||
"cmprb %0,1,%1,%2"
|
||||
[(set_attr "type" "logical")])
|
||||
|
||||
;; Test byte membership within set of 8 bytes.
|
||||
;;
|
||||
;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
;; represents a byte whose value is ignored in this context and
|
||||
;; vv, the least significant byte, holds the byte value that is to
|
||||
;; be tested for membership within the set specified by operand 2.
|
||||
;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||
;;
|
||||
;; Return in target register operand 0 a value of 1 if vv equals one
|
||||
;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
|
||||
;; register operand 0 to 0. Note that the 8 byte values held within
|
||||
;; operand 2 need not be unique.
|
||||
;;
|
||||
;; Though the instructions to which this expansion maps operate on
|
||||
;; 64-bit registers, the current implementation requires that operands
|
||||
;; 0 and 1 have mode SI as the high-order bits provide no information
|
||||
;; that is not already available in the low-order bits. To avoid the
|
||||
;; costs of data widening operations, future enhancements might allow
|
||||
;; DI mode for operand 0 and/or might allow operand 1 to be QI mode.
|
||||
(define_expand "cmpeqb"
|
||||
[(set (match_dup 3)
|
||||
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||
UNSPEC_CMPEQB))
|
||||
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(if_then_else:SI (lt (match_dup 3)
|
||||
(const_int 0))
|
||||
(const_int -1)
|
||||
(if_then_else (gt (match_dup 3)
|
||||
(const_int 0))
|
||||
(const_int 1)
|
||||
(const_int 0))))]
|
||||
"TARGET_P9_MISC && TARGET_64BIT"
|
||||
{
|
||||
operands[3] = gen_reg_rtx (CCmode);
|
||||
})
|
||||
|
||||
;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx
|
||||
;; represents a byte whose value is ignored in this context and
|
||||
;; vv, the least significant byte, holds the byte value that is to
|
||||
;; be tested for membership within the set specified by operand 2.
|
||||
;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
|
||||
;;
|
||||
;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv
|
||||
;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
|
||||
;; set the GT bit to zero. The other 3 bits of the target CR register
|
||||
;; are all set to 0.
|
||||
(define_insn "*cmpeqb_internal"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=y")
|
||||
(unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r")]
|
||||
UNSPEC_CMPEQB))]
|
||||
"TARGET_P9_MISC && TARGET_64BIT"
|
||||
"cmpeqb %0,%1,%2"
|
||||
[(set_attr "type" "logical")])
|
||||
|
||||
|
||||
(include "sync.md")
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user