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FRV docs
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@ -1,3 +1,8 @@
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2002-12-06 Bernd Schmidt <bernds@redhat.com>
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* doc/invoke.texi: Document FRV port options.
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* doc/md.texi: Document FRV register classes.
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2002-12-07 Gerald Pfeifer <pfeifer@dbai.tuwien.ac.at>
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* doc/install.texi (Configuration): Improve description of cases
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@ -678,6 +678,19 @@ in the following sections.
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-mtarget-align -mno-target-align @gol
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-mlongcalls -mno-longcalls}
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@emph{FRV Options}
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@gccoptlist{
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-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 -mhard-float -msoft-float @gol
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-malloc-cc -mfixed-cc -mdword -mno-dword -mdouble -mno-double @gol
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-mmedia -mno-media -mmuladd -mno-muladd -mlibrary-pic -macc-4 @gol
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-macc-8 -mpack -mno-pack -mno-eflags -mcond-move -mno-cond-move @gol
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-mscc -mno-scc -mcond-exec -mno-cond-exec -mvliw-branch -mno-vliw-branch @gol
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-mmulti-cond-exec -mno-multi-cond-exec -mnested-cond-exec @gol
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-mno-nested-cond-exec -mtomcat-stats @gol
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-mcpu=@var{cpu}}
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@item Code Generation Options
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@xref{Code Gen Options,,Options for Code Generation Conventions}.
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@gccoptlist{
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@ -5214,6 +5227,7 @@ that macro, which enables you to change the defaults.
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* PDP-11 Options::
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* Xstormy16 Options::
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* Xtensa Options::
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* FRV Options::
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@end menu
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@node M680x0 Options
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@ -9939,6 +9953,233 @@ These options are defined for Xstormy16:
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Choose startup files and linker script suitable for the simulator.
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@end table
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@node FRV Options
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@subsection FRV Options
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@cindex FRV Options
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@table @gcctabopt
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@item -mgpr-32
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@opindex mgpr-32
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Only use the first 32 general purpose registers.
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@item -mgpr-64
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@opindex mgpr-64
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Use all 64 general purpose registers.
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@item -mfpr-32
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@opindex mfpr-32
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Use only the first 32 floating point registers.
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@item -mfpr-64
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@opindex mfpr-64
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Use all 64 floating point registers
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@item -mhard-float
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@opindex mhard-float
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Use hardware instructions for floating point operations.
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@item -msoft-float
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@opindex msoft-float
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Use library routines for floating point operations.
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@item -malloc-cc
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@opindex malloc-cc
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Dynamically allocate condition code registers.
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@item -mfixed-cc
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@opindex mfixed-cc
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Do not try to dynamically allocate condition code registers, only
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use @code{icc0} and @code{fcc0}.
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@item -mdword
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@opindex mdword
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Change ABI to use double word insns.
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@item -mno-dword
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@opindex mno-dword
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Do not use double word instructions.
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@item -mdouble
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@opindex mdouble
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Use floating point double instructions.
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@item -mno-double
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@opindex mno-double
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Do not use floating point double instructions.
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@item -mmedia
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@opindex mmedia
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Use media instructions.
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@item -mno-media
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@opindex mno-media
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Do not use media instructions.
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@item -mmuladd
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@opindex mmuladd
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Use multiply and add/subtract instructions.
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@item -mno-muladd
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@opindex mno-muladd
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Do not use multiply and add/subtract instructions.
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@item -mlibrary-pic
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@opindex mlibrary-pic
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Enable PIC support for building libraries
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@item -macc-4
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@opindex macc-4
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Use only the first four media accumulator registers.
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@item -macc-8
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@opindex macc-8
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Use all eight media accumulator registers.
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@item -mpack
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@opindex mpack
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Pack VLIW instructions.
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@item -mno-pack
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@opindex mno-pack
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Do not pack VLIW instructions.
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@item -mno-eflags
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@opindex mno-eflags
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Do not mark ABI switches in e_flags.
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@item -mcond-move
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@opindex mcond-move
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Enable the use of conditional-move instructions (default).
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mno-cond-move
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@opindex mno-cond-move
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Disable the use of conditional-move instructions.
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mscc
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@opindex mscc
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Enable the use of conditional set instructions (default).
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mno-scc
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@opindex mno-scc
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Disable the use of conditional set instructions.
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mcond-exec
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@opindex mcond-exec
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Enable the use of conditional execution (default).
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mno-cond-exec
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@opindex mno-cond-exec
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Disable the use of conditional execution.
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mvliw-branch
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@opindex mvliw-branch
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Run a pass to pack branches into VLIW instructions (default).
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mno-vliw-branch
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@opindex mno-vliw-branch
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Do not run a pass to pack branches into VLIW instructions.
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mmulti-cond-exec
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@opindex mmulti-cond-exec
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Enable optimization of @code{&&} and @code{||} in conditional execution
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(default).
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mno-multi-cond-exec
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@opindex mno-multi-cond-exec
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Disable optimization of @code{&&} and @code{||} in conditional execution.
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mnested-cond-exec
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@opindex mnested-cond-exec
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Enable nested conditional execution optimizations (default).
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mno-nested-cond-exec
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@opindex mno-nested-cond-exec
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Disable nested conditional execution optimizations.
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This switch is mainly for debugging the compiler and will likely be removed
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in a future version.
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@item -mtomcat-stats
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@opindex mtomcat-stats
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Cause gas to print out tomcat statistics.
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@item -mcpu=@var{cpu}
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@opindex mcpu
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Select the processor type for which to generate code. Possible values are
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@samp{simple}, @samp{tomcat}, @samp{fr500}, @samp{fr400}, @samp{fr300},
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@samp{frv}.
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@end table
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@node Xtensa Options
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@subsection Xtensa Options
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@cindex Xtensa Options
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@ -1750,6 +1750,98 @@ Integer constant in the range 1 to 4 for @code{shladd} instruction
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Memory operand except postincrement and postdecrement
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@end table
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@item FRV---@file{frv.h}
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@table @code
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@item a
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Register in the class ACC_REGS (@code{acc0} to @code{acc7}).
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@item b
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Register in the class EVEN_ACC_REGS (@code{acc0} to @code{acc7}).
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@item c
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Register in the class CC_REGS (@code{fcc0} to @code{fcc3} and @code{icc0} to @code{icc3}).
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@item d
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Register in the class GPR_REGS (@code{gr0} to @code{gr63}).
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@item e
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Register in the class EVEN_REGS (@code{gr0} to @code{gr63}).
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Odd registers are excluded not in the class but through the use of a machine
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mode larger than 4 bytes.
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@item f
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Register in the class FPR_REGS (@code{fr0} to @code{fr63}).
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@item h
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Register in the class FEVEN_REGS (@code{fr0} to @code{fr63}).
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Odd registers are excluded not in the class but through the use of a machine
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mode larger than 4 bytes.
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@item l
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Register in the class LR_REG (the @code{lr} register).
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@item q
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Register in the class QUAD_REGS (@code{gr2} to @code{gr63}).
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Register numbers not divisible by 4 are excluded not in the class but through
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the use of a machine mode larger than 8 bytes.
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@item t
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Register in the class ICC_REGS@ (@code{icc0} to @code{icc3}).
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@item u
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Register in the class FCC_REGS (@code{fcc0} to @code{fcc3}).
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@item v
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Register in the class ICR_REGS (@code{cc4} to @code{cc7}).
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@item w
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Register in the class FCR_REGS (@code{cc0} to @code{cc3}).
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@item x
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Register in the class QUAD_FPR_REGS (@code{fr0} to @code{fr63}).
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Register numbers not divisible by 4 are excluded not in the class but through
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the use of a machine mode larger than 8 bytes.
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@item z
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Register in the class SPR_REGS (@code{lcr} and @code{lr}).
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@item A
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Register in the class QUAD_ACC_REGS (@code{acc0} to @code{acc7}).
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@item B
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Register in the class ACCG_REGS (@code{accg0} to @code{accg7}).
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@item C
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Register in the class CR_REGS (@code{cc0} to @code{cc7}).
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@item G
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Floating point constant zero
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@item I
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6-bit signed integer constant
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@item J
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10-bit signed integer constant
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@item L
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16-bit signed integer constant
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@item M
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16-bit unsigned integer constant
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@item N
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12-bit signed integer constant that is negative - i.e. in the
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range of -2048 to -1
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@item O
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Constant zero
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@item P
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12-bit signed integer constant that is greater than zero - i.e. in the
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range of 1 to 2047.
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@end table
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@item IP2K---@file{ip2k.h}
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@table @code
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@item a
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