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Enable shrink wrapping for the RISC-V target.
This commit implements the target macros (TARGET_SHRINK_WRAP_*) that
enable separate shrink wrapping for function prologues/epilogues in
RISC-V.
Tested against SPEC CPU 2017, this change always has a net-positive
effect on the dynamic instruction count. See the following table for
the breakdown on how this reduces the number of dynamic instructions
per workload on a like-for-like (i.e., same config file; suppressing
shrink-wrapping with -fno-shrink-wrap):
# dynamic instructions
w/o shrink-wrap w/ shrink-wrap reduction
500.perlbench_r 1265716786593 1262156218578 3560568015 0.28%
500.perlbench_r 779224795689 765337009025 13887786664 1.78%
500.perlbench_r 724087331471 711307152522 12780178949 1.77%
502.gcc_r 204259864844 194517006339 9742858505 4.77%
502.gcc_r 244047794302 231555834722 12491959580 5.12%
502.gcc_r 230896069400 221877703011 9018366389 3.91%
502.gcc_r 192130616624 183856450605 8274166019 4.31%
502.gcc_r 258875074079 247756203226 11118870853 4.30%
505.mcf_r 662653430325 660678680547 1974749778 0.30%
520.omnetpp_r 985114167068 934191310154 50922856914 5.17%
523.xalancbmk_r 927037633578 921688937650 5348695928 0.58%
525.x264_r 490953958454 490565583447 388375007 0.08%
525.x264_r 1994662294421 1993171932425 1490361996 0.07%
525.x264_r 1897617120450 1896062750609 1554369841 0.08%
531.deepsjeng_r 1695189878907 1669304130411 25885748496 1.53%
541.leela_r 1925941222222 1897900861198 28040361024 1.46%
548.exchange2_r 2073816227944 2073816226729 1215 0.00%
557.xz_r 379572090003 379057409041 514680962 0.14%
557.xz_r 953117469352 952680431430 437037922 0.05%
557.xz_r 536859579650 536456690164 402889486 0.08%
18421773405376 18223938521833 197834883543 1.07% totals
Signed-off-by: Manolis Tsamis <manolis.tsamis@vrull.eu>
gcc/ChangeLog:
* config/riscv/riscv.cc (struct machine_function): Add array to store
register wrapping information.
(riscv_for_each_saved_reg): Skip registers that are wrapped separetely.
(riscv_get_separate_components): New function.
(riscv_components_for_bb): Likewise.
(riscv_disqualify_components): Likewise.
(riscv_process_components): Likewise.
(riscv_emit_prologue_components): Likewise.
(riscv_emit_epilogue_components): Likewise.
(riscv_set_handled_components): Likewise.
(TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define.
(TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise.
(TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/shrink-wrap-1.c: New test.
This commit is contained in:
mtsamis
Philipp Tomsich
parent
06c8f2ebf0
commit
705bae2351
@ -26,6 +26,7 @@ along with GCC; see the file COPYING3. If not see
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#include "system.h"
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#include "coretypes.h"
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#include "target.h"
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#include "backend.h"
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#include "tm.h"
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#include "rtl.h"
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#include "regs.h"
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@ -51,6 +52,7 @@ along with GCC; see the file COPYING3. If not see
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#include "optabs.h"
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#include "bitmap.h"
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#include "df.h"
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#include "function-abi.h"
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#include "diagnostic.h"
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#include "builtins.h"
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#include "predict.h"
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@ -154,6 +156,11 @@ struct GTY(()) machine_function {
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/* The current frame information, calculated by riscv_compute_frame_info. */
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struct riscv_frame_info frame;
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/* The components already handled by separate shrink-wrapping, which should
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not be considered by the prologue and epilogue. */
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bool reg_is_wrapped_separately[FIRST_PSEUDO_REGISTER];
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};
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/* Information about a single argument. */
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@ -4806,7 +4813,7 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn,
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for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
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if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
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{
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bool handle_reg = TRUE;
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bool handle_reg = !cfun->machine->reg_is_wrapped_separately[regno];
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/* If this is a normal return in a function that calls the eh_return
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builtin, then do not restore the eh return data registers as that
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@ -4837,9 +4844,11 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn,
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for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
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if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
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{
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bool handle_reg = !cfun->machine->reg_is_wrapped_separately[regno];
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machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode;
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riscv_save_restore_reg (mode, regno, offset, fn);
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if (handle_reg)
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riscv_save_restore_reg (mode, regno, offset, fn);
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offset -= GET_MODE_SIZE (mode).to_constant ();
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}
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}
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@ -5321,6 +5330,162 @@ riscv_epilogue_uses (unsigned int regno)
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return false;
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}
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/* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
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static sbitmap
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riscv_get_separate_components (void)
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{
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HOST_WIDE_INT offset;
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sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER);
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bitmap_clear (components);
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if (riscv_use_save_libcall (&cfun->machine->frame)
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|| cfun->machine->interrupt_handler_p)
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return components;
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offset = cfun->machine->frame.gp_sp_offset.to_constant ();
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for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
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if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
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{
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/* We can only wrap registers that have small operand offsets.
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For large offsets a pseudo register might be needed which
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cannot be created during the shrink wrapping pass. */
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if (SMALL_OPERAND (offset))
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bitmap_set_bit (components, regno);
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offset -= UNITS_PER_WORD;
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}
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offset = cfun->machine->frame.fp_sp_offset.to_constant ();
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for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
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if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
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{
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machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode;
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/* We can only wrap registers that have small operand offsets.
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For large offsets a pseudo register might be needed which
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cannot be created during the shrink wrapping pass. */
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if (SMALL_OPERAND (offset))
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bitmap_set_bit (components, regno);
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offset -= GET_MODE_SIZE (mode).to_constant ();
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}
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/* Don't mess with the hard frame pointer. */
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if (frame_pointer_needed)
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bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
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bitmap_clear_bit (components, RETURN_ADDR_REGNUM);
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return components;
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}
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/* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
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static sbitmap
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riscv_components_for_bb (basic_block bb)
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{
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bitmap in = DF_LIVE_IN (bb);
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bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
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bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
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sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER);
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bitmap_clear (components);
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function_abi_aggregator callee_abis;
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rtx_insn *insn;
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FOR_BB_INSNS (bb, insn)
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if (CALL_P (insn))
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callee_abis.note_callee_abi (insn_callee_abi (insn));
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HARD_REG_SET extra_caller_saves = callee_abis.caller_save_regs (*crtl->abi);
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/* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
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for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
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if (!fixed_regs[regno]
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&& !crtl->abi->clobbers_full_reg_p (regno)
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&& (TEST_HARD_REG_BIT (extra_caller_saves, regno)
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|| bitmap_bit_p (in, regno)
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|| bitmap_bit_p (gen, regno)
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|| bitmap_bit_p (kill, regno)))
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bitmap_set_bit (components, regno);
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for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
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if (!fixed_regs[regno]
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&& !crtl->abi->clobbers_full_reg_p (regno)
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&& (TEST_HARD_REG_BIT (extra_caller_saves, regno)
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|| bitmap_bit_p (in, regno)
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|| bitmap_bit_p (gen, regno)
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|| bitmap_bit_p (kill, regno)))
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bitmap_set_bit (components, regno);
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return components;
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}
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/* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
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static void
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riscv_disqualify_components (sbitmap, edge, sbitmap, bool)
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{
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/* Nothing to do for riscv. */
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}
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static void
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riscv_process_components (sbitmap components, bool prologue_p)
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{
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HOST_WIDE_INT offset;
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riscv_save_restore_fn fn = prologue_p? riscv_save_reg : riscv_restore_reg;
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offset = cfun->machine->frame.gp_sp_offset.to_constant ();
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for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
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if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
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{
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if (bitmap_bit_p (components, regno))
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riscv_save_restore_reg (word_mode, regno, offset, fn);
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offset -= UNITS_PER_WORD;
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}
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offset = cfun->machine->frame.fp_sp_offset.to_constant ();
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for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
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if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
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{
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machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode;
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if (bitmap_bit_p (components, regno))
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riscv_save_restore_reg (mode, regno, offset, fn);
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offset -= GET_MODE_SIZE (mode).to_constant ();
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}
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}
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/* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
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static void
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riscv_emit_prologue_components (sbitmap components)
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{
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riscv_process_components (components, true);
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}
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/* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
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static void
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riscv_emit_epilogue_components (sbitmap components)
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{
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riscv_process_components (components, false);
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}
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static void
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riscv_set_handled_components (sbitmap components)
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{
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for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
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if (bitmap_bit_p (components, regno))
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cfun->machine->reg_is_wrapped_separately[regno] = true;
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for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
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if (bitmap_bit_p (components, regno))
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cfun->machine->reg_is_wrapped_separately[regno] = true;
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}
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/* Return nonzero if this function is known to have a null epilogue.
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This allows the optimizer to omit jumps to jumps if no stack
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was created. */
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@ -6684,6 +6849,30 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
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#undef TARGET_FUNCTION_ARG_BOUNDARY
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#define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
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#undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
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#define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
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riscv_get_separate_components
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#undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
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#define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
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riscv_components_for_bb
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#undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
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#define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
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riscv_disqualify_components
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#undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
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#define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
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riscv_emit_prologue_components
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#undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
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#define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
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riscv_emit_epilogue_components
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#undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
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#define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
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riscv_set_handled_components
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/* The generic ELF target does not always have TLS support. */
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#ifdef HAVE_AS_TLS
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#undef TARGET_HAVE_TLS
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24
gcc/testsuite/gcc.target/riscv/shrink-wrap-1.c
Normal file
24
gcc/testsuite/gcc.target/riscv/shrink-wrap-1.c
Normal file
@ -0,0 +1,24 @@
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/* { dg-do compile } */
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/* { dg-options "-fshrink-wrap" } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz" } } */
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void g(void);
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void f(int x)
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{
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if (x)
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{
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/* Force saving of some callee-saved registers. With shrink wrapping
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enabled these only need to be saved if x is non-zero. */
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register int s2 asm("18") = x;
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register int s3 asm("19") = x;
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register int s4 asm("20") = x;
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asm("" : : "r"(s2));
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asm("" : : "r"(s3));
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asm("" : : "r"(s4));
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g();
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}
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}
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/* The resulting code should do nothing if X is 0. */
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/* { dg-final { scan-assembler "bne\ta0,zero,.*\n.*ret" } } */
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