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mips.c (machine_function): Add new fields: ignore_hazard_length_p and all_noreorder_p.
* config/mips/mips.c (machine_function): Add new fields: ignore_hazard_length_p and all_noreorder_p. (mips_flag_delayed_branch): New variable. (override_options): Treat '/' as an operand punctuation character. Set up mips_flag_delayed_branch. (print_operand): Handle '/'. (mips_output_function_prologue): Put the whole function in .set noreorder and .set nomacro if all_noreorder_p is true. (mips_output_function_epilogue): End the noreorder/nomacro sequence. (mips16_optimize_gp): Remove "first insn" parameter. (mips16_lay_out_constants): New function, split out from mips_reorg. (mips_avoid_hazard, mips_avoid_hazards): New functions. (mips_reorg): For mips16 code, call mips16_lay_out_constant and (optionally) mips16_optimize. If TARGET_EXPLICIT_RELOCS, do delayed-branch scheduling followed by hazard detection. (mips_adjust_insn_length): Only account for hazards if !ignore_hazard_length_p. (mips_output_load_label): Add a nop to the o32 sequence if the target suffers from load delays. (mips_output_conditional_branch): Add %/ to the end of branches. (mips_output_division): Fill the branch delay slot with %#. * config/mips/mips.md: Remove redundant '%*' from mips16 branch instructions. End all other %* branches with %/. (ffssi2, ffsdi2): Fix lengths. (truncdisi2, truncdihi2, truncdiqi2): Add store attributes. (fix_truncdfsi2_macro): Turn off .set nomacro if appropriate. (fix_truncsfsi2_macro): Likewise. (mov_lwl): Set hazard to "none". (ashldi3_internal): Fill the branch delay slot with %#. (ashrdi3_internal, lshrdi3_internal): Likewise. (exception_receiver): Explicitly set $28. (hazard_nop): New pattern. From-SVN: r68821
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
0184bd46b0
commit
6f2993e58b
@ -1,3 +1,38 @@
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2003-07-02 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (machine_function): Add new fields:
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ignore_hazard_length_p and all_noreorder_p.
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(mips_flag_delayed_branch): New variable.
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(override_options): Treat '/' as an operand punctuation character.
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Set up mips_flag_delayed_branch.
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(print_operand): Handle '/'.
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(mips_output_function_prologue): Put the whole function in
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.set noreorder and .set nomacro if all_noreorder_p is true.
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(mips_output_function_epilogue): End the noreorder/nomacro sequence.
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(mips16_optimize_gp): Remove "first insn" parameter.
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(mips16_lay_out_constants): New function, split out from mips_reorg.
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(mips_avoid_hazard, mips_avoid_hazards): New functions.
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(mips_reorg): For mips16 code, call mips16_lay_out_constant
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and (optionally) mips16_optimize. If TARGET_EXPLICIT_RELOCS,
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do delayed-branch scheduling followed by hazard detection.
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(mips_adjust_insn_length): Only account for hazards if
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!ignore_hazard_length_p.
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(mips_output_load_label): Add a nop to the o32 sequence if
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the target suffers from load delays.
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(mips_output_conditional_branch): Add %/ to the end of branches.
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(mips_output_division): Fill the branch delay slot with %#.
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* config/mips/mips.md: Remove redundant '%*' from mips16 branch
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instructions. End all other %* branches with %/.
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(ffssi2, ffsdi2): Fix lengths.
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(truncdisi2, truncdihi2, truncdiqi2): Add store attributes.
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(fix_truncdfsi2_macro): Turn off .set nomacro if appropriate.
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(fix_truncsfsi2_macro): Likewise.
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(mov_lwl): Set hazard to "none".
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(ashldi3_internal): Fill the branch delay slot with %#.
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(ashrdi3_internal, lshrdi3_internal): Likewise.
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(exception_receiver): Explicitly set $28.
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(hazard_nop): New pattern.
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Wed Jul 2 08:12:36 CEST 2003 Jan Hubicka <jh@suse.cz>
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* cgraphunit.c (cgraph_finalize_unit): Set current_function_decl
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@ -243,13 +243,17 @@ static void save_restore_insns PARAMS ((int, rtx, long));
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static void mips_gp_insn PARAMS ((rtx, rtx));
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static void mips16_fp_args PARAMS ((FILE *, int, int));
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static void build_mips16_function_stub PARAMS ((FILE *));
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static void mips16_optimize_gp PARAMS ((rtx));
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static void mips16_optimize_gp PARAMS ((void));
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static rtx add_constant PARAMS ((struct constant **,
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rtx,
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enum machine_mode));
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static void dump_constants PARAMS ((struct constant *,
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rtx));
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static rtx mips_find_symbol PARAMS ((rtx));
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static void mips16_lay_out_constants PARAMS ((void));
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static void mips_avoid_hazard PARAMS ((rtx, rtx, int *,
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rtx *, rtx));
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static void mips_avoid_hazards PARAMS ((void));
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static void mips_reorg PARAMS ((void));
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static void abort_with_insn PARAMS ((rtx, const char *))
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ATTRIBUTE_NORETURN;
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@ -335,6 +339,14 @@ struct machine_function GTY(()) {
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/* The register to use as the global pointer within this function. */
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unsigned int global_pointer;
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/* True if mips_adjust_insn_length should ignore an instruction's
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hazard attribute. */
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bool ignore_hazard_length_p;
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/* True if the whole function is suitable for .set noreorder and
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.set nomacro. */
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bool all_noreorder_p;
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};
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/* Information about a single argument. */
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@ -585,6 +597,9 @@ int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
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/* An alias set for the GOT. */
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static int mips_got_alias_set;
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/* A copy of the original flag_delayed_branch: see override_options. */
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static int mips_flag_delayed_branch;
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static GTY (()) int mips_output_filename_first_time = 1;
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/* Hardware names for the registers. If -mrnames is used, this
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@ -5153,6 +5168,14 @@ override_options ()
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else
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mips16 = 0;
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/* When using explicit relocs, we call dbr_schedule from within
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mips_reorg. */
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if (TARGET_EXPLICIT_RELOCS)
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{
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mips_flag_delayed_branch = flag_delayed_branch;
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flag_delayed_branch = 0;
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}
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real_format_for_mode[SFmode - QFmode] = &mips_single_format;
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real_format_for_mode[DFmode - QFmode] = &mips_double_format;
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#ifdef MIPS_TFMODE_FORMAT
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@ -5163,6 +5186,7 @@ override_options ()
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mips_print_operand_punct['?'] = 1;
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mips_print_operand_punct['#'] = 1;
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mips_print_operand_punct['/'] = 1;
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mips_print_operand_punct['&'] = 1;
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mips_print_operand_punct['!'] = 1;
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mips_print_operand_punct['*'] = 1;
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@ -5478,6 +5502,7 @@ mips_debugger_offset (addr, offset)
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'*' Turn on both .set noreorder and .set nomacro if filling delay slots
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'!' Turn on .set nomacro if filling delay slots
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'#' Print nop if in a .set noreorder section.
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'/' Like '#', but does nothing within a delayed branch sequence
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'?' Print 'l' if we are to use a branch likely instead of normal branch.
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'@' Print the name of the assembler temporary register (at or $1).
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'.' Print the name of the register with a hard-wired zero (zero or $0).
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@ -5551,6 +5576,14 @@ print_operand (file, op, letter)
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fputs ("\n\tnop", file);
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break;
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case '/':
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/* Print an extra newline so that the delayed insn is separated
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from the following ones. This looks neater and is consistent
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with non-nop delayed sequences. */
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if (set_noreorder != 0 && final_sequence == 0)
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fputs ("\n\tnop\n", file);
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break;
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case '(':
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if (set_noreorder++ == 0)
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fputs (".set\tnoreorder\n\t", file);
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@ -7073,10 +7106,16 @@ mips_output_function_prologue (file, size)
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fprintf (file, "\n");
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}
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/* Handle the initialization of $gp for SVR4 PIC. */
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if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
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fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
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reg_names[PIC_FUNCTION_ADDR_REGNUM]);
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{
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/* Handle the initialization of $gp for SVR4 PIC. */
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if (!cfun->machine->all_noreorder_p)
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output_asm_insn ("%(.cpload\t%^%)", 0);
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else
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output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
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}
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else if (cfun->machine->all_noreorder_p)
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output_asm_insn ("%(%<", 0);
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}
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/* Emit an instruction to move SRC into DEST. When generating
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@ -7487,6 +7526,14 @@ mips_output_function_epilogue (file, size)
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{
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rtx string;
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if (cfun->machine->all_noreorder_p)
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{
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/* Avoid using %>%) since it adds excess whitespace. */
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output_asm_insn (".set\tmacro", 0);
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output_asm_insn (".set\treorder", 0);
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set_noreorder = set_nomacro = 0;
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}
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#ifndef FUNCTION_NAME_ALREADY_DECLARED
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if (!flag_inhibit_size_directive)
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{
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@ -8893,8 +8940,7 @@ build_mips16_call_stub (retval, fn, arg_size, fp_code)
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generated is correct, so we do not need to catch all cases. */
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static void
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mips16_optimize_gp (first)
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rtx first;
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mips16_optimize_gp ()
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{
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rtx gpcopy, slot, insn;
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@ -8907,7 +8953,7 @@ mips16_optimize_gp (first)
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gpcopy = NULL_RTX;
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slot = NULL_RTX;
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for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
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for (insn = get_insns (); insn != NULL_RTX; insn = next_active_insn (insn))
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{
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rtx set;
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@ -8990,7 +9036,7 @@ mips16_optimize_gp (first)
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#if 0
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/* ??? FIXME. Rewrite for new UNSPEC_RELOC stuff. */
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for (insn = first; insn != NULL_RTX; insn = next)
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for (insn = get_insns (); insn != NULL_RTX; insn = next)
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{
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rtx set1, set2;
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@ -9059,7 +9105,7 @@ mips16_optimize_gp (first)
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replace all assignments from SLOT to GPCOPY with assignments from
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$28. */
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for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
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for (insn = get_insns (); insn != NULL_RTX; insn = next_active_insn (insn))
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{
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rtx set;
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@ -9236,22 +9282,14 @@ mips_find_symbol (addr)
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PC relative loads that are out of range. */
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static void
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mips_reorg ()
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mips16_lay_out_constants ()
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{
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int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
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rtx first, insn;
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struct constant *constants;
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if (! TARGET_MIPS16)
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return;
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first = get_insns ();
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/* If $gp is used, try to remove stores, and replace loads with
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copies from $gp. */
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if (optimize)
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mips16_optimize_gp (first);
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/* Scan the function looking for PC relative loads which may be out
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of range. All such loads will either be from the constant table,
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or be getting the address of a constant string. If the size of
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@ -9436,6 +9474,144 @@ mips_reorg ()
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constant table, but we have no way to prevent that. */
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}
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/* Subroutine of mips_reorg. If there is a hazard between INSN
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and a previous instruction, avoid it by inserting nops after
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instruction AFTER.
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*DELAYED_REG and *HILO_DELAY describe the hazards that apply at
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this point. If *DELAYED_REG is non-null, INSN must wait a cycle
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before using the value of that register. *HILO_DELAY counts the
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number of instructions since the last hilo hazard (that is,
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the number of instructions since the last mflo or mfhi).
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After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
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for the next instruction.
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LO_REG is an rtx for the LO register, used in dependence checking. */
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static void
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mips_avoid_hazard (after, insn, hilo_delay, delayed_reg, lo_reg)
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rtx after, insn, *delayed_reg, lo_reg;
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int *hilo_delay;
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{
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rtx pattern, set;
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int nops, ninsns;
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if (!INSN_P (insn))
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return;
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pattern = PATTERN (insn);
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/* Do not put the whole function in .set noreorder if it contains
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an asm statement. We don't know whether there will be hazards
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between the asm statement and the gcc-generated code. */
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if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
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cfun->machine->all_noreorder_p = false;
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/* Ignore zero-length instructions (barriers and the like). */
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ninsns = get_attr_length (insn) / 4;
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if (ninsns == 0)
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return;
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/* Work out how many nops are needed. Note that we only care about
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registers that are explicitly mentioned in the instruction's pattern.
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It doesn't matter that calls use the argument registers or that they
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clobber hi and lo. */
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if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
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nops = 2 - *hilo_delay;
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else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
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nops = 1;
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else
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nops = 0;
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/* Insert the nops between this instruction and the previous one.
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Each new nop takes us further from the last hilo hazard. */
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*hilo_delay += nops;
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while (nops-- > 0)
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emit_insn_after (gen_hazard_nop (), after);
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/* Set up the state for the next instruction. */
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*hilo_delay += ninsns;
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*delayed_reg = 0;
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if (INSN_CODE (insn) >= 0)
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switch (get_attr_hazard (insn))
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{
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case HAZARD_NONE:
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break;
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case HAZARD_HILO:
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*hilo_delay = 0;
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break;
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case HAZARD_DELAY:
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set = single_set (insn);
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if (set == 0)
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abort ();
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*delayed_reg = SET_DEST (set);
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break;
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}
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}
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/* Go through the instruction stream and insert nops where necessary.
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See if the whole function can then be put into .set noreorder &
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.set nomacro. */
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static void
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mips_avoid_hazards ()
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{
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rtx insn, last_insn, lo_reg, delayed_reg;
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int hilo_delay, i;
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/* Recalculate instruction lengths without taking nops into account. */
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cfun->machine->ignore_hazard_length_p = true;
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shorten_branches (get_insns ());
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/* The profiler code uses assembler macros. */
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cfun->machine->all_noreorder_p = !current_function_profile;
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last_insn = 0;
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hilo_delay = 2;
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delayed_reg = 0;
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lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
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for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
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if (INSN_P (insn))
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{
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if (GET_CODE (PATTERN (insn)) == SEQUENCE)
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for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
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mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
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&hilo_delay, &delayed_reg, lo_reg);
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else
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mips_avoid_hazard (last_insn, insn, &hilo_delay,
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&delayed_reg, lo_reg);
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last_insn = insn;
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}
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}
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/* Implement TARGET_MACHINE_DEPENDENT_REORG. */
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static void
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mips_reorg ()
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{
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if (TARGET_MIPS16)
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{
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if (optimize)
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mips16_optimize_gp ();
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mips16_lay_out_constants ();
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}
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else if (TARGET_EXPLICIT_RELOCS)
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{
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if (mips_flag_delayed_branch)
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dbr_schedule (get_insns (), rtl_dump_file);
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mips_avoid_hazards ();
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}
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}
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/* Return a number assessing the cost of moving a register in class
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FROM to class TO. The classes are expressed using the enumeration
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values such as `GENERAL_REGS'. A value of 2 is the default; other
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@ -9551,7 +9727,7 @@ mips_adjust_insn_length (insn, length)
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length += 4;
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/* See how many nops might be needed to avoid hardware hazards. */
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if (INSN_CODE (insn) >= 0)
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if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
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switch (get_attr_hazard (insn))
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{
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case HAZARD_NONE:
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@ -9590,6 +9766,8 @@ mips_output_load_label ()
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return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
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default:
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if (ISA_HAS_LOAD_DELAY)
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return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
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return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
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}
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else
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@ -9709,10 +9887,10 @@ mips_output_conditional_branch (insn,
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case 8:
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/* Just a simple conditional branch. */
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if (float_p)
|
||||
sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
|
||||
sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
|
||||
inverted_p ? inverted_comp : comp);
|
||||
else
|
||||
sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
|
||||
sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
|
||||
inverted_p ? inverted_comp : comp,
|
||||
need_z_p ? "z" : "",
|
||||
op1,
|
||||
@ -9930,7 +10108,7 @@ mips_output_division (division, operands)
|
||||
if (TARGET_MIPS16)
|
||||
return "bnez\t%2,1f\n\tbreak\t7\n1:";
|
||||
else
|
||||
return "bne\t%2,%.,1f\n\t%#break\t7\n1:";
|
||||
return "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
|
||||
}
|
||||
return division;
|
||||
}
|
||||
|
||||
@ -3040,7 +3040,7 @@ move\\t%0,%z4\\n\\
|
||||
}"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "length" "12")])
|
||||
(set_attr "length" "28")])
|
||||
|
||||
(define_insn "ffsdi2"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&d")
|
||||
@ -3074,7 +3074,7 @@ move\\t%0,%z4\\n\\
|
||||
}"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "DI")
|
||||
(set_attr "length" "24")])
|
||||
(set_attr "length" "28")])
|
||||
|
||||
|
||||
|
||||
@ -3489,7 +3489,7 @@ move\\t%0,%z4\\n\\
|
||||
"@
|
||||
sll\t%0,%1,0
|
||||
sw\t%1,%0"
|
||||
[(set_attr "type" "darith")
|
||||
[(set_attr "type" "darith,store")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "extended_mips16" "yes,*")])
|
||||
|
||||
@ -3500,7 +3500,7 @@ move\\t%0,%z4\\n\\
|
||||
"@
|
||||
sll\t%0,%1,0
|
||||
sh\t%1,%0"
|
||||
[(set_attr "type" "darith")
|
||||
[(set_attr "type" "darith,store")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "extended_mips16" "yes,*")])
|
||||
|
||||
@ -3511,7 +3511,7 @@ move\\t%0,%z4\\n\\
|
||||
"@
|
||||
sll\t%0,%1,0
|
||||
sb\t%1,%0"
|
||||
[(set_attr "type" "darith")
|
||||
[(set_attr "type" "darith,store")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "extended_mips16" "yes,*")])
|
||||
|
||||
@ -4075,7 +4075,11 @@ move\\t%0,%z4\\n\\
|
||||
(fix:SI (match_operand:DF 1 "register_operand" "f")))
|
||||
(clobber (match_scratch:DF 2 "=d"))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
|
||||
"trunc.w.d %0,%1,%2"
|
||||
{
|
||||
if (set_nomacro)
|
||||
return ".set\tmacro\n\ttrunc.w.d %0,%1,%2\n\t.set\tmacro";
|
||||
return "trunc.w.d %0,%1,%2";
|
||||
}
|
||||
[(set_attr "type" "fcvt")
|
||||
(set_attr "mode" "DF")
|
||||
(set_attr "length" "36")])
|
||||
@ -4106,7 +4110,11 @@ move\\t%0,%z4\\n\\
|
||||
(fix:SI (match_operand:SF 1 "register_operand" "f")))
|
||||
(clobber (match_scratch:SF 2 "=d"))]
|
||||
"TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
|
||||
"trunc.w.s %0,%1,%2"
|
||||
{
|
||||
if (set_nomacro)
|
||||
return ".set\tmacro\n\ttrunc.w.s %0,%1,%2\n\t.set\tmacro";
|
||||
return "trunc.w.s %0,%1,%2";
|
||||
}
|
||||
[(set_attr "type" "fcvt")
|
||||
(set_attr "mode" "DF")
|
||||
(set_attr "length" "36")])
|
||||
@ -4437,7 +4445,8 @@ move\\t%0,%z4\\n\\
|
||||
"!TARGET_MIPS16"
|
||||
"lwl\t%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "mode" "SI")])
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "hazard" "none")])
|
||||
|
||||
(define_insn "mov_lwr"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
@ -5636,7 +5645,7 @@ move\\t%0,%z4\\n\\
|
||||
operands[4] = const0_rtx;
|
||||
|
||||
return \"sll\\t%3,%2,26\\n\\
|
||||
\\tbgez\\t%3,1f\\n\\
|
||||
\\tbgez\\t%3,1f%#\\n\\
|
||||
\\tsll\\t%M0,%L1,%2\\n\\
|
||||
\\t%(b\\t3f\\n\\
|
||||
\\tmove\\t%L0,%z4%)\\n\\
|
||||
@ -5991,7 +6000,7 @@ move\\t%0,%z4\\n\\
|
||||
operands[4] = const0_rtx;
|
||||
|
||||
return \"sll\\t%3,%2,26\\n\\
|
||||
\\tbgez\\t%3,1f\\n\\
|
||||
\\tbgez\\t%3,1f%#\\n\\
|
||||
\\tsra\\t%L0,%M1,%2\\n\\
|
||||
\\t%(b\\t3f\\n\\
|
||||
\\tsra\\t%M0,%M1,31%)\\n\\
|
||||
@ -6369,7 +6378,7 @@ move\\t%0,%z4\\n\\
|
||||
operands[4] = const0_rtx;
|
||||
|
||||
return \"sll\\t%3,%2,26\\n\\
|
||||
\\tbgez\\t%3,1f\\n\\
|
||||
\\tbgez\\t%3,1f%#\\n\\
|
||||
\\tsrl\\t%L0,%M1,%2\\n\\
|
||||
\\t%(b\\t3f\\n\\
|
||||
\\tmove\\t%M0,%z4%)\\n\\
|
||||
@ -6988,16 +6997,16 @@ move\\t%0,%z4\\n\\
|
||||
if (operands[2] != pc_rtx)
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return \"%*b%C0z\\t%1,%2\";
|
||||
return \"b%C0z\\t%1,%2\";
|
||||
else
|
||||
return \"%*bt%C0z\\t%2\";
|
||||
return \"bt%C0z\\t%2\";
|
||||
}
|
||||
else
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return \"%*b%N0z\\t%1,%3\";
|
||||
return \"b%N0z\\t%1,%3\";
|
||||
else
|
||||
return \"%*bt%N0z\\t%3\";
|
||||
return \"bt%N0z\\t%3\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
@ -7017,16 +7026,16 @@ move\\t%0,%z4\\n\\
|
||||
if (operands[2] != pc_rtx)
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return \"%*b%C0z\\t%1,%2\";
|
||||
return \"b%C0z\\t%1,%2\";
|
||||
else
|
||||
return \"%*bt%C0z\\t%2\";
|
||||
return \"bt%C0z\\t%2\";
|
||||
}
|
||||
else
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
return \"%*b%N0z\\t%1,%3\";
|
||||
return \"b%N0z\\t%1,%3\";
|
||||
else
|
||||
return \"%*bt%N0z\\t%3\";
|
||||
return \"bt%N0z\\t%3\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
@ -8389,15 +8398,15 @@ move\\t%0,%z4\\n\\
|
||||
if (flag_pic && ! TARGET_EMBEDDED_PIC)
|
||||
{
|
||||
if (get_attr_length (insn) <= 8)
|
||||
return \"%*b\\t%l0\";
|
||||
return \"%*b\\t%l0%/\";
|
||||
else
|
||||
{
|
||||
output_asm_insn (mips_output_load_label (), operands);
|
||||
return \"%*jr\\t%@%]\";
|
||||
return \"%*jr\\t%@%/%]\";
|
||||
}
|
||||
}
|
||||
else
|
||||
return \"%*j\\t%l0\";
|
||||
return \"%*j\\t%l0%/\";
|
||||
}"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
@ -8450,14 +8459,14 @@ move\\t%0,%z4\\n\\
|
||||
(define_insn "indirect_jump_internal1"
|
||||
[(set (pc) (match_operand:SI 0 "register_operand" "d"))]
|
||||
"!(Pmode == DImode)"
|
||||
"%*j\\t%0"
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
(define_insn "indirect_jump_internal2"
|
||||
[(set (pc) (match_operand:DI 0 "register_operand" "d"))]
|
||||
"Pmode == DImode"
|
||||
"%*j\\t%0"
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
@ -8501,7 +8510,7 @@ move\\t%0,%z4\\n\\
|
||||
(match_operand:SI 0 "register_operand" "d"))
|
||||
(use (label_ref (match_operand 1 "" "")))]
|
||||
""
|
||||
"%*j\\t%0"
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
@ -8510,7 +8519,7 @@ move\\t%0,%z4\\n\\
|
||||
(match_operand:DI 0 "register_operand" "d"))
|
||||
(use (label_ref (match_operand 1 "" "")))]
|
||||
"TARGET_64BIT"
|
||||
"%*j\\t%0"
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
@ -8626,7 +8635,7 @@ move\\t%0,%z4\\n\\
|
||||
(clobber (reg:SI 31))]
|
||||
"TARGET_EMBEDDED_PIC"
|
||||
"%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
|
||||
lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "24")])
|
||||
@ -8643,7 +8652,7 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(clobber (reg:DI 31))]
|
||||
"TARGET_EMBEDDED_PIC"
|
||||
"%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
|
||||
ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")
|
||||
(set_attr "length" "24")])
|
||||
@ -8751,7 +8760,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(define_insn "return"
|
||||
[(return)]
|
||||
"mips_can_use_return_insn ()"
|
||||
"%*j\\t$31"
|
||||
"%*j\t$31%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
@ -8761,10 +8770,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
[(use (match_operand 0 "pmode_register_operand" ""))
|
||||
(return)]
|
||||
""
|
||||
"*
|
||||
{
|
||||
return \"%*j\\t%0\";
|
||||
}"
|
||||
"%*j\t%0%/"
|
||||
[(set_attr "type" "jump")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
@ -8827,7 +8833,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
}")
|
||||
|
||||
(define_insn "exception_receiver"
|
||||
[(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER)]
|
||||
[(set (reg:SI 28)
|
||||
(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER))]
|
||||
"TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
|
||||
{ return mips_restore_gp (operands); }
|
||||
[(set_attr "type" "load")
|
||||
@ -8867,8 +8874,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(match_operand 1 "" ""))]
|
||||
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
%*jr\\t%0
|
||||
%*j\\t%0"
|
||||
%*jr\t%0%/
|
||||
%*j\t%0%/"
|
||||
[(set_attr "type" "call")])
|
||||
|
||||
(define_expand "sibcall_value"
|
||||
@ -8889,8 +8896,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(match_operand 2 "" "")))]
|
||||
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
%*jr\\t%1
|
||||
%*j\\t%1"
|
||||
%*jr\t%1%/
|
||||
%*j\t%1%/"
|
||||
[(set_attr "type" "call")])
|
||||
|
||||
(define_insn "sibcall_value_multiple_internal"
|
||||
@ -8902,8 +8909,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(match_dup 2)))]
|
||||
"TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
|
||||
"@
|
||||
%*jr\\t%1
|
||||
%*j\\t%1"
|
||||
%*jr\t%1%/
|
||||
%*j\t%1%/"
|
||||
[(set_attr "type" "call")])
|
||||
|
||||
(define_expand "call"
|
||||
@ -8922,7 +8929,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(match_operand 1 "" ""))
|
||||
(clobber (reg:SI 31))]
|
||||
""
|
||||
"%*jal\\t%0"
|
||||
"%*jal\t%0%/"
|
||||
"reload_completed && TARGET_SPLIT_CALLS"
|
||||
[(const_int 0)]
|
||||
{
|
||||
@ -8939,7 +8946,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(clobber (reg:SI 31))
|
||||
(const_int 1)]
|
||||
"TARGET_SPLIT_CALLS"
|
||||
"%*jalr\\t%0"
|
||||
"%*jalr\t%0%/"
|
||||
[(set_attr "type" "call")])
|
||||
|
||||
(define_expand "call_value"
|
||||
@ -8960,7 +8967,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(match_operand 2 "" "")))
|
||||
(clobber (reg:SI 31))]
|
||||
""
|
||||
"%*jal\\t%1"
|
||||
"%*jal\t%1%/"
|
||||
"reload_completed && TARGET_SPLIT_CALLS"
|
||||
[(const_int 0)]
|
||||
{
|
||||
@ -8979,7 +8986,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(clobber (reg:SI 31))
|
||||
(const_int 1)]
|
||||
"TARGET_SPLIT_CALLS"
|
||||
"%*jalr\\t%1"
|
||||
"%*jalr\t%1%/"
|
||||
[(set_attr "type" "call")])
|
||||
|
||||
(define_insn_and_split "call_value_multiple_internal"
|
||||
@ -8991,7 +8998,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(match_dup 2)))
|
||||
(clobber (reg:SI 31))]
|
||||
""
|
||||
"%*jal\\t%1"
|
||||
"%*jal\t%1%/"
|
||||
"reload_completed && TARGET_SPLIT_CALLS"
|
||||
[(const_int 0)]
|
||||
{
|
||||
@ -9013,7 +9020,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(clobber (reg:SI 31))
|
||||
(const_int 1)]
|
||||
"TARGET_SPLIT_CALLS"
|
||||
"%*jalr\\t%1"
|
||||
"%*jalr\t%1%/"
|
||||
[(set_attr "type" "call")])
|
||||
|
||||
;; Call subroutine returning any type.
|
||||
@ -9100,6 +9107,18 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
[(set_attr "type" "nop")
|
||||
(set_attr "mode" "none")])
|
||||
|
||||
;; Like nop, but commented out when outside a .set noreorder block.
|
||||
(define_insn "hazard_nop"
|
||||
[(const_int 1)]
|
||||
""
|
||||
{
|
||||
if (set_noreorder)
|
||||
return "nop";
|
||||
else
|
||||
return "#nop";
|
||||
}
|
||||
[(set_attr "type" "arith")])
|
||||
|
||||
;; The MIPS chip does not seem to require stack probes.
|
||||
;;
|
||||
;; (define_expand "probe"
|
||||
@ -9509,9 +9528,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
"*
|
||||
{
|
||||
if (operands[3] != pc_rtx)
|
||||
return \"%*b%C2z\\t%1,%3\";
|
||||
return \"b%C2z\\t%1,%3\";
|
||||
else
|
||||
return \"%*b%N2z\\t%1,%4\";
|
||||
return \"b%N2z\\t%1,%4\";
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "mode" "none")
|
||||
@ -9534,9 +9553,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
"*
|
||||
{
|
||||
if (operands[3] != pc_rtx)
|
||||
return \"%*b%C2z\\t%1,%3\";
|
||||
return \"b%C2z\\t%1,%3\";
|
||||
else
|
||||
return \"%*b%N2z\\t%1,%4\";
|
||||
return \"b%N2z\\t%1,%4\";
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "mode" "none")
|
||||
@ -9563,9 +9582,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
"*
|
||||
{
|
||||
if (operands[3] != pc_rtx)
|
||||
return \"%*bt%C2z\\t%3\";
|
||||
return \"bt%C2z\\t%3\";
|
||||
else
|
||||
return \"%*bt%N2z\\t%4\";
|
||||
return \"bt%N2z\\t%4\";
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "mode" "none")
|
||||
@ -9588,9 +9607,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
"*
|
||||
{
|
||||
if (operands[3] != pc_rtx)
|
||||
return \"%*bt%C2z\\t%3\";
|
||||
return \"bt%C2z\\t%3\";
|
||||
else
|
||||
return \"%*bt%N2z\\t%4\";
|
||||
return \"bt%N2z\\t%4\";
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "mode" "none")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user