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[AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions

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* config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF.
	* config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>):
	Use h_con constraint for operand 1.
	(*aarch64_fnma4_elt_from_dup<mode>): Likewise.
	(*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2.

From-SVN: r246189
This commit is contained in:
Kyrylo Tkachov 2017-03-16 10:03:11 +00:00 committed by Kyrylo Tkachov
parent f5a3ad8ae5
commit 6d06971da1
3 changed files with 13 additions and 5 deletions

8
gcc/ChangeLog

@ -1,3 +1,11 @@
2017-03-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF.
* config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>):
Use h_con constraint for operand 1.
(*aarch64_fnma4_elt_from_dup<mode>): Likewise.
(*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2.
2017-03-15 Jeff Law <law@redhat.com>
PR tree-optimization/71437

6
gcc/config/aarch64/aarch64-simd.md

@ -1647,7 +1647,7 @@
[(set (match_operand:VMUL 0 "register_operand" "=w")
(fma:VMUL
(vec_duplicate:VMUL
(match_operand:<VEL> 1 "register_operand" "w"))
(match_operand:<VEL> 1 "register_operand" "<h_con>"))
(match_operand:VMUL 2 "register_operand" "w")
(match_operand:VMUL 3 "register_operand" "0")))]
"TARGET_SIMD"
@ -1726,7 +1726,7 @@
(neg:VMUL
(match_operand:VMUL 2 "register_operand" "w"))
(vec_duplicate:VMUL
(match_operand:<VEL> 1 "register_operand" "w"))
(match_operand:<VEL> 1 "register_operand" "<h_con>"))
(match_operand:VMUL 3 "register_operand" "0")))]
"TARGET_SIMD"
"fmls\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
@ -3178,7 +3178,7 @@
(unspec:VHSDF
[(match_operand:VHSDF 1 "register_operand" "w")
(vec_duplicate:VHSDF
(match_operand:<VEL> 2 "register_operand" "w"))]
(match_operand:<VEL> 2 "register_operand" "<h_con>"))]
UNSPEC_FMULX))]
"TARGET_SIMD"
"fmulx\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]";

4
gcc/config/aarch64/iterators.md

@ -749,11 +749,11 @@
(DF "to_128") (V2DF "to_64")])
;; For certain vector-by-element multiplication instructions we must
;; constrain the HI cases to use only V0-V15. This is covered by
;; constrain the 16-bit cases to use only V0-V15. This is covered by
;; the 'x' constraint. All other modes may use the 'w' constraint.
(define_mode_attr h_con [(V2SI "w") (V4SI "w")
(V4HI "x") (V8HI "x")
(V4HF "w") (V8HF "w")
(V4HF "x") (V8HF "x")
(V2SF "w") (V4SF "w")
(V2DF "w") (DF "w")])