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aix43.h (TARGET_DEFAULT): Delete MASK_NEW_MNEMONICS.

Browse Source 
2012-08-15  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/
	* config/rs6000/aix43.h (TARGET_DEFAULT): Delete MASK_NEW_MNEMONICS.
	(RS6000_CALL_GLUE): Adjust for single assembler syntax.
	* config/rs6000/aix51.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
	Ditto.
	* config/rs6000/aix52.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
	Ditto.
	* config/rs6000/aix53.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
	Ditto.
	* config/rs6000/aix61.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
	Ditto.
	* config/rs6000/darwin.h (TARGET_DEFAULT): Ditto.
	* config/rs6000/darwin.md (whole file): Adjust to single
	assembler syntax.
	* config/rs6000/darwin64.h (TARGET_DEFAULT): Delete
	MASK_NEW_MNEMONICS.
	* config/rs6000/default64.h (TARGET_DEFAULT): Ditto.
	* config/rs6000/dfp.md: (whole file): Adjust to single
	assembler syntax.
	* config/rs6000/eabi.h (TARGET_DEFAULT): Delete
	MASK_NEW_MNEMONICS.
	* config/rs6000/eabialtivec.h (TARGET_DEFAULT): Ditto.
	* config/rs6000/eabispe.h (TARGET_DEFAULT): Ditto.
	* config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Ditto.
	* config/rs6000/linuxspe.h (TARGET_DEFAULT): Ditto.
	* config/rs6000/rs6000-cpus.def (whole file): Delete
	POWERPC_BASE_MASK.
	* config/rs6000/rs6000-tables.opt: Regenerate.
	* config/rs6000/rs6000.c (POWERPC_BASE_MASK): Delete.
	(num_insns_constant_wide): Adjust comments.
	(whole file): Adjust to single assembler syntax.
	(output_cbranch): Adjust comment.
	* config/rs6000/rs6000.h (ASSEMBLER_DIALECT): Delete.
	* config/rs6000/rs6000.md: (whole file): Adjust to single
	assembler syntax.
	* config/rs6000/rs6000.opt (mnew-mnemonics): Delete.
	(mold-mnemonics): Delete.
	* config/rs6000/spe.md: (whole file): Adjust to single
	assembler syntax.
	* config/rs6000/sync.md: (whole file): Adjust to single
	assembler syntax.
	* config/rs6000/sysv4.h (TARGET_DEFAULT): Delete
	MASK_NEW_MNEMONICS.
	(ASM_OUTPUT_REG_PUSH): Adjust.
	(ASM_OUTPUT_REG_POP): Adjust.
	* config/rs6000/sysv4le.h (TARGET_DEFAULT): Delete
	MASK_NEW_MNEMONICS.
	* config/rs6000/vsx.md: (whole file): Adjust to single
	assembler syntax.
	* config/rs6000/vxworks.h (TARGET_DEFAULT): Delete
	MASK_NEW_MNEMONICS.
	* doc/invoke.texi: Adjust documentation to reflect the
	removal of -mnew-mnemonics and -mold-mnemonics.

libgcc/
	* longlong.h: (whole file, powerpc): Adjust to single assembler syntax.

From-SVN: r190432
This commit is contained in:
Segher Boessenkool 2012-08-16 03:34:27 +02:00 committed by Segher Boessenkool
parent a441dedbc4
commit 6b39bc38c8
31 changed files with 550 additions and 550 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
gcc/ChangeLog
View File

@ -1,3 +1,58 @@
2012-08-15 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/aix43.h (TARGET_DEFAULT): Delete MASK_NEW_MNEMONICS.
(RS6000_CALL_GLUE): Adjust for single assembler syntax.
* config/rs6000/aix51.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
Ditto.
* config/rs6000/aix52.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
Ditto.
* config/rs6000/aix53.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
Ditto.
* config/rs6000/aix61.h (TARGET_DEFAULT, RS6000_CALL_GLUE):
Ditto.
* config/rs6000/darwin.h (TARGET_DEFAULT): Ditto.
* config/rs6000/darwin.md (whole file): Adjust to single
assembler syntax.
* config/rs6000/darwin64.h (TARGET_DEFAULT): Delete
MASK_NEW_MNEMONICS.
* config/rs6000/default64.h (TARGET_DEFAULT): Ditto.
* config/rs6000/dfp.md: (whole file): Adjust to single
assembler syntax.
* config/rs6000/eabi.h (TARGET_DEFAULT): Delete
MASK_NEW_MNEMONICS.
* config/rs6000/eabialtivec.h (TARGET_DEFAULT): Ditto.
* config/rs6000/eabispe.h (TARGET_DEFAULT): Ditto.
* config/rs6000/linuxaltivec.h (TARGET_DEFAULT): Ditto.
* config/rs6000/linuxspe.h (TARGET_DEFAULT): Ditto.
* config/rs6000/rs6000-cpus.def (whole file): Delete
POWERPC_BASE_MASK.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.c (POWERPC_BASE_MASK): Delete.
(num_insns_constant_wide): Adjust comments.
(whole file): Adjust to single assembler syntax.
(output_cbranch): Adjust comment.
* config/rs6000/rs6000.h (ASSEMBLER_DIALECT): Delete.
* config/rs6000/rs6000.md: (whole file): Adjust to single
assembler syntax.
* config/rs6000/rs6000.opt (mnew-mnemonics): Delete.
(mold-mnemonics): Delete.
* config/rs6000/spe.md: (whole file): Adjust to single
assembler syntax.
* config/rs6000/sync.md: (whole file): Adjust to single
assembler syntax.
* config/rs6000/sysv4.h (TARGET_DEFAULT): Delete
MASK_NEW_MNEMONICS.
(ASM_OUTPUT_REG_PUSH): Adjust.
(ASM_OUTPUT_REG_POP): Adjust.
* config/rs6000/sysv4le.h (TARGET_DEFAULT): Delete
MASK_NEW_MNEMONICS.
* config/rs6000/vsx.md: (whole file): Adjust to single
assembler syntax.
* config/rs6000/vxworks.h (TARGET_DEFAULT): Delete
MASK_NEW_MNEMONICS.
* doc/invoke.texi: Adjust documentation to reflect the
removal of -mnew-mnemonics and -mold-mnemonics.
2012-08-15 Segher Boessenkool <segher@kernel.crashing.org>
* common/config/rs6000/rs6000-common.c (rs6000_handle_option):

4
gcc/config/rs6000/aix43.h
View File

@ -93,7 +93,7 @@ do { \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
@ -146,7 +146,7 @@ do { \
and "cror 31,31,31" for POWER architecture. */
#undef RS6000_CALL_GLUE
#define RS6000_CALL_GLUE "{cror 31,31,31|nop}"
#define RS6000_CALL_GLUE "nop"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */

4
gcc/config/rs6000/aix51.h
View File

@ -90,7 +90,7 @@ do { \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604e
@ -150,7 +150,7 @@ do { \
and "cror 31,31,31" for POWER architecture. */
#undef RS6000_CALL_GLUE
#define RS6000_CALL_GLUE "{cror 31,31,31|nop}"
#define RS6000_CALL_GLUE "nop"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */

4
gcc/config/rs6000/aix52.h
View File

@ -99,7 +99,7 @@ do { \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER4
@ -162,7 +162,7 @@ do { \
and "cror 31,31,31" for POWER architecture. */
#undef RS6000_CALL_GLUE
#define RS6000_CALL_GLUE "{cror 31,31,31|nop}"
#define RS6000_CALL_GLUE "nop"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */

4
gcc/config/rs6000/aix53.h
View File

@ -105,7 +105,7 @@ do { \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER5
@ -160,7 +160,7 @@ do { \
and "cror 31,31,31" for POWER architecture. */
#undef RS6000_CALL_GLUE
#define RS6000_CALL_GLUE "{cror 31,31,31|nop}"
#define RS6000_CALL_GLUE "nop"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */

4
gcc/config/rs6000/aix61.h
View File

@ -106,7 +106,7 @@ do { \
%{pthread: -D_THREAD_SAFE}"
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#define TARGET_DEFAULT 0
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_POWER7
@ -161,7 +161,7 @@ do { \
and "cror 31,31,31" for POWER architecture. */
#undef RS6000_CALL_GLUE
#define RS6000_CALL_GLUE "{cror 31,31,31|nop}"
#define RS6000_CALL_GLUE "nop"
/* AIX 4.2 and above provides initialization and finalization function
support from linker command line. */

2
gcc/config/rs6000/darwin.h
View File

@ -280,7 +280,7 @@ extern int darwin_emit_branch_islands;
default as well. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_NEW_MNEMONICS | MASK_PPC_GFXOPT)
#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT)
/* Darwin only runs on PowerPC, so short-circuit POWER patterns. */
#undef TARGET_IEEEQUAD

36
gcc/config/rs6000/darwin.md
View File

@ -1,5 +1,5 @@
/* Machine description patterns for PowerPC running Darwin (Mac OS X).
Copyright (C) 2004, 2005, 2007, 2010, 2011 Free Software Foundation, Inc.
Copyright (C) 2004-2012 Free Software Foundation, Inc.
Contributed by Apple Computer Inc.
This file is part of GCC.
@ -23,7 +23,7 @@ You should have received a copy of the GNU General Public License
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
(high:DI (match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT"
"{cau|addis} %0,%1,ha16(%2)"
"addis %0,%1,ha16(%2)"
[(set_attr "length" "4")])
(define_insn "movdf_low_si"
@ -44,9 +44,9 @@ You should have received a copy of the GNU General Public License
return \"ld %0,lo16(%2)(%1)\";
else
{
output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
return (\"{l|lwz} %0,0(%0)\");
output_asm_insn (\"la %0,lo16(%2)(%1)\", operands);
output_asm_insn (\"lwz %L0,4(%0)\", operands);
return (\"lwz %0,0(%0)\");
}
}
default:
@ -102,7 +102,7 @@ You should have received a copy of the GNU General Public License
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
{l|lwz} %0,lo16(%2)(%1)"
lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
@ -113,7 +113,7 @@ You should have received a copy of the GNU General Public License
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"@
lfs %0,lo16(%2)(%1)
{l|lwz} %0,lo16(%2)(%1)"
lwz %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
@ -124,7 +124,7 @@ You should have received a copy of the GNU General Public License
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
{st|stw} %0,lo16(%2)(%1)"
stw %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@ -135,7 +135,7 @@ You should have received a copy of the GNU General Public License
"TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
"@
stfs %0,lo16(%2)(%1)
{st|stw} %0,lo16(%2)(%1)"
stw %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@ -146,7 +146,7 @@ You should have received a copy of the GNU General Public License
(match_operand 2 "" ""))))]
"TARGET_MACHO && TARGET_64BIT"
"@
{l|ld} %0,lo16(%2)(%1)
ld %0,lo16(%2)(%1)
lfd %0,lo16(%2)(%1)"
[(set_attr "type" "load")
(set_attr "length" "4")])
@ -156,7 +156,7 @@ You should have received a copy of the GNU General Public License
(match_operand 2 "" "")))
(match_operand:SI 0 "gpc_reg_operand" "r"))]
"TARGET_MACHO && ! TARGET_64BIT"
"{st|stw} %0,lo16(%2)(%1)"
"stw %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@ -166,7 +166,7 @@ You should have received a copy of the GNU General Public License
(match_operand:DI 0 "gpc_reg_operand" "r,*!d"))]
"TARGET_MACHO && TARGET_64BIT"
"@
{st|std} %0,lo16(%2)(%1)
std %0,lo16(%2)(%1)
stfd %0,lo16(%2)(%1)"
[(set_attr "type" "store")
(set_attr "length" "4")])
@ -189,14 +189,14 @@ You should have received a copy of the GNU General Public License
[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
(high:SI (match_operand 1 "" "")))]
"TARGET_MACHO && ! TARGET_64BIT"
"{liu|lis} %0,ha16(%1)")
"lis %0,ha16(%1)")
(define_insn "macho_high_di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
(high:DI (match_operand 1 "" "")))]
"TARGET_MACHO && TARGET_64BIT"
"{liu|lis} %0,ha16(%1)")
"lis %0,ha16(%1)")
(define_expand "macho_low"
[(set (match_operand 0 "" "")
@ -218,8 +218,8 @@ You should have received a copy of the GNU General Public License
(match_operand 2 "" "")))]
"TARGET_MACHO && ! TARGET_64BIT"
"@
{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
la %0,lo16(%2)(%1)
addic %0,%1,lo16(%2)")
(define_insn "macho_low_di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@ -227,8 +227,8 @@ You should have received a copy of the GNU General Public License
(match_operand 2 "" "")))]
"TARGET_MACHO && TARGET_64BIT"
"@
{cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
{cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
la %0,lo16(%2)(%1)
addic %0,%1,lo16(%2)")
(define_split
[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")

2
gcc/config/rs6000/darwin64.h
View File

@ -20,7 +20,7 @@
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \
| MASK_MULTIPLE | MASK_NEW_MNEMONICS | MASK_PPC_GFXOPT)
| MASK_MULTIPLE | MASK_PPC_GFXOPT)
#undef DARWIN_ARCH_SPEC
#define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}"

3
gcc/config/rs6000/default64.h
View File

@ -19,5 +19,4 @@ along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS)
#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_64BIT)

24
gcc/config/rs6000/dfp.md
View File

@ -68,12 +68,12 @@
&& (TARGET_HARD_FLOAT && TARGET_FPRS)"
"@
mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0
fmr %0,%1
mt%0 %1
mf%1 %0
{cror 0,0,0|nop}
nop
#
#"
[(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*")
@ -89,14 +89,14 @@
mr %0,%1
mt%0 %1
mf%1 %0
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0
{lil|li} %0,%1
{liu|lis} %0,%v1
{cal|la} %0,%a1
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0
li %0,%1
lis %0,%v1
la %0,%a1
#
#
{cror 0,0,0|nop}"
nop"
[(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])
@ -335,7 +335,7 @@
stfd%U0%X0 %1,%0
mt%0 %1
mf%1 %0
{cror 0,0,0|nop}
nop
#
#
#
@ -361,7 +361,7 @@
stfd%U0%X0 %1,%0
mt%0 %1
mf%1 %0
{cror 0,0,0|nop}
nop
#
#
#"
@ -383,7 +383,7 @@
#
#
#
{cror 0,0,0|nop}"
nop"
[(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")])

2
gcc/config/rs6000/eabi.h
View File

@ -21,7 +21,7 @@
/* Add -meabi to target flags. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI)
#define TARGET_DEFAULT MASK_EABI
/* Invoke an initializer function to set up the GOT. */
#define NAME__MAIN "__eabi"

2
gcc/config/rs6000/eabialtivec.h
View File

@ -21,7 +21,7 @@
/* Add -meabi and -maltivec to target flags. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI | MASK_ALTIVEC)
#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1

2
gcc/config/rs6000/eabispe.h
View File

@ -20,7 +20,7 @@
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI)
#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

2
gcc/config/rs6000/linuxaltivec.h
View File

@ -21,7 +21,7 @@
/* Override rs6000.h and sysv4.h definition. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_ALTIVEC)
#define TARGET_DEFAULT MASK_ALTIVEC
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS rs6000_altivec_abi = 1

2
gcc/config/rs6000/linuxspe.h
View File

@ -21,7 +21,7 @@
/* Override rs6000.h and sysv4.h definition. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
#define TARGET_DEFAULT MASK_STRICT_ALIGN
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

121
gcc/config/rs6000/rs6000-cpus.def
View File

@ -32,101 +32,78 @@
where the arguments are the fields of struct rs6000_ptt. */
RS6000_CPU ("401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405,
POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440,
POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476", PROCESSOR_PPC476,
POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF
| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
| MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK)
RS6000_CPU ("601", PROCESSOR_PPC601,
POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING)
RS6000_CPU ("602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("476fp", PROCESSOR_PPC476,
MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
| MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
| MASK_ISEL)
RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB
| MASK_CMPB | MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT
| MASK_ISEL)
MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
| MASK_NO_UPDATE)
RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
| MASK_PPC_GFXOPT | MASK_ISEL)
MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
| MASK_MFCRF | MASK_ISEL)
RS6000_CPU ("860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
RS6000_CPU ("970", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("cell", PROCESSOR_CELL,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT)
RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
RS6000_CPU ("G5", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
RS6000_CPU ("titan", PROCESSOR_TITAN,
POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT
RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF)
RS6000_CPU ("power5", PROCESSOR_POWER5,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT
RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
RS6000_CPU ("power5+", PROCESSOR_POWER5,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT
RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
RS6000_CPU ("power6", PROCESSOR_POWER6,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT
RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
RS6000_CPU ("power6x", PROCESSOR_POWER6,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT
RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
| MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
RS6000_CPU ("power7", PROCESSOR_POWER7, /* Don't add MASK_ISEL by default */
POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
| MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
| MASK_VSX | MASK_RECIP_PRECISION)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("rs64", PROCESSOR_RS64A,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)

33
gcc/config/rs6000/rs6000-tables.opt
View File

@ -141,50 +141,47 @@ EnumValue
Enum(rs6000_cpu_opt_value) String(cell) Value(37)
EnumValue
Enum(rs6000_cpu_opt_value) String(common) Value(38)
Enum(rs6000_cpu_opt_value) String(ec603e) Value(38)
EnumValue
Enum(rs6000_cpu_opt_value) String(ec603e) Value(39)
Enum(rs6000_cpu_opt_value) String(G3) Value(39)
EnumValue
Enum(rs6000_cpu_opt_value) String(G3) Value(40)
Enum(rs6000_cpu_opt_value) String(G4) Value(40)
EnumValue
Enum(rs6000_cpu_opt_value) String(G4) Value(41)
Enum(rs6000_cpu_opt_value) String(G5) Value(41)
EnumValue
Enum(rs6000_cpu_opt_value) String(G5) Value(42)
Enum(rs6000_cpu_opt_value) String(titan) Value(42)
EnumValue
Enum(rs6000_cpu_opt_value) String(titan) Value(43)
Enum(rs6000_cpu_opt_value) String(power3) Value(43)
EnumValue
Enum(rs6000_cpu_opt_value) String(power3) Value(44)
Enum(rs6000_cpu_opt_value) String(power4) Value(44)
EnumValue
Enum(rs6000_cpu_opt_value) String(power4) Value(45)
Enum(rs6000_cpu_opt_value) String(power5) Value(45)
EnumValue
Enum(rs6000_cpu_opt_value) String(power5) Value(46)
Enum(rs6000_cpu_opt_value) String(power5+) Value(46)
EnumValue
Enum(rs6000_cpu_opt_value) String(power5+) Value(47)
Enum(rs6000_cpu_opt_value) String(power6) Value(47)
EnumValue
Enum(rs6000_cpu_opt_value) String(power6) Value(48)
Enum(rs6000_cpu_opt_value) String(power6x) Value(48)
EnumValue
Enum(rs6000_cpu_opt_value) String(power6x) Value(49)
Enum(rs6000_cpu_opt_value) String(power7) Value(49)
EnumValue
Enum(rs6000_cpu_opt_value) String(power7) Value(50)
Enum(rs6000_cpu_opt_value) String(powerpc) Value(50)
EnumValue
Enum(rs6000_cpu_opt_value) String(powerpc) Value(51)
Enum(rs6000_cpu_opt_value) String(powerpc64) Value(51)
EnumValue
Enum(rs6000_cpu_opt_value) String(powerpc64) Value(52)
EnumValue
Enum(rs6000_cpu_opt_value) String(rs64) Value(53)
Enum(rs6000_cpu_opt_value) String(rs64) Value(52)

62
gcc/config/rs6000/rs6000.c
View File

@ -1457,8 +1457,7 @@ static const struct attribute_spec rs6000_attribute_table[] =
/* Simplifications for entries below. */
enum {
POWERPC_BASE_MASK = MASK_NEW_MNEMONICS,
POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC
};
/* Some OSs don't support saving the high part of 64-bit registers on context
@ -1468,7 +1467,7 @@ enum {
the user's specification. */
enum {
POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN
| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
| MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
| MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
@ -4023,11 +4022,11 @@ direct_return (void)
int
num_insns_constant_wide (HOST_WIDE_INT value)
{
/* signed constant loadable with {cal|addi} */
/* signed constant loadable with addi */
if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
return 1;
/* constant loadable with {cau|addis} */
/* constant loadable with addis */
else if ((value & 0xffff) == 0
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
@ -13027,7 +13026,7 @@ rs6000_output_load_multiple (rtx operands[3])
rtx xop[10];
if (XVECLEN (operands[0], 0) == 1)
return "{l|lwz} %2,0(%1)";
return "lwz %2,0(%1)";
for (i = 0; i < words; i++)
if (refers_to_regno_p (REGNO (operands[2]) + i,
@ -13038,7 +13037,7 @@ rs6000_output_load_multiple (rtx operands[3])
xop[0] = GEN_INT (4 * (words-1));
xop[1] = operands[1];
xop[2] = operands[2];
output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop);
return "";
}
else if (i == 0)
@ -13046,7 +13045,7 @@ rs6000_output_load_multiple (rtx operands[3])
xop[0] = GEN_INT (4 * (words-1));
xop[1] = operands[1];
xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop);
return "";
}
else
@ -13057,16 +13056,16 @@ rs6000_output_load_multiple (rtx operands[3])
xop[0] = GEN_INT (j * 4);
xop[1] = operands[1];
xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
output_asm_insn ("lwz %2,%0(%1)", xop);
}
xop[0] = GEN_INT (i * 4);
xop[1] = operands[1];
output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
output_asm_insn ("lwz %1,%0(%1)", xop);
return "";
}
}
return "{lsi|lswi} %2,%1,%N0";
return "lswi %2,%1,%N0";
}
@ -14957,7 +14956,7 @@ print_operand (FILE *file, rtx x, int code)
&& REGNO (x) != CTR_REGNO))
output_operand_lossage ("invalid %%T value");
else if (REGNO (x) == LR_REGNO)
fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
fputs ("lr", file);
else
fputs ("ctr", file);
return;
@ -15922,8 +15921,7 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn)
gcc_unreachable ();
}
/* Maybe we have a guess as to how likely the branch is.
The old mnemonics don't have a way to specify this information. */
/* Maybe we have a guess as to how likely the branch is. */
pred = "";
note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
if (note != NULL_RTX)
@ -15950,9 +15948,9 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn)
}
if (label == NULL)
s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
s += sprintf (s, "b%slr%s ", ccode, pred);
else
s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
s += sprintf (s, "b%s%s ", ccode, pred);
/* We need to escape any '%' characters in the reg_names string.
Assume they'd only be the first character.... */
@ -18788,9 +18786,9 @@ output_probe_stack_range (rtx reg1, rtx reg2)
xops[0] = reg1;
xops[1] = reg2;
if (TARGET_64BIT)
output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops);
output_asm_insn ("cmpd 0,%0,%1", xops);
else
output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops);
output_asm_insn ("cmpw 0,%0,%1", xops);
fputs ("\tbeq 0,", asm_out_file);
assemble_name_raw (asm_out_file, end_lab);
@ -18798,11 +18796,11 @@ output_probe_stack_range (rtx reg1, rtx reg2)
/* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
xops[1] = GEN_INT (-PROBE_INTERVAL);
output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops);
output_asm_insn ("addi %0,%0,%1", xops);
/* Probe at TEST_ADDR and branch. */
xops[1] = gen_rtx_REG (Pmode, 0);
output_asm_insn ("{st|stw} %1,0(%0)", xops);
output_asm_insn ("stw %1,0(%0)", xops);
fprintf (asm_out_file, "\tb ");
assemble_name_raw (asm_out_file, loop_lab);
fputc ('\n', asm_out_file);
@ -22351,7 +22349,7 @@ output_function_profiler (FILE *file, int labelno)
fprintf (file, "\tmflr %s\n", reg_names[0]);
if (NO_PROFILE_COUNTERS)
{
asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
asm_fprintf (file, "\tstw %s,4(%s)\n",
reg_names[0], reg_names[1]);
}
else if (TARGET_SECURE_PLT && flag_pic)
@ -22364,29 +22362,29 @@ output_function_profiler (FILE *file, int labelno)
}
else
asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
asm_fprintf (file, "\tstw %s,4(%s)\n",
reg_names[0], reg_names[1]);
asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
asm_fprintf (file, "\t{cau|addis} %s,%s,",
asm_fprintf (file, "\taddis %s,%s,",
reg_names[12], reg_names[12]);
assemble_name (file, buf);
asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
assemble_name (file, buf);
asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
}
else if (flag_pic == 1)
{
fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
asm_fprintf (file, "\tstw %s,4(%s)\n",
reg_names[0], reg_names[1]);
asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
asm_fprintf (file, "\tlwz %s,", reg_names[0]);
assemble_name (file, buf);
asm_fprintf (file, "@got(%s)\n", reg_names[12]);
}
else if (flag_pic > 1)
{
asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
asm_fprintf (file, "\tstw %s,4(%s)\n",
reg_names[0], reg_names[1]);
/* Now, we need to get the address of the label. */
if (TARGET_LINK_STACK)
@ -22407,19 +22405,19 @@ output_function_profiler (FILE *file, int labelno)
fputs ("-.\n1:", file);
asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
}
asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
asm_fprintf (file, "\tlwz %s,0(%s)\n",
reg_names[0], reg_names[11]);
asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
asm_fprintf (file, "\tadd %s,%s,%s\n",
reg_names[0], reg_names[0], reg_names[11]);
}
else
{
asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
asm_fprintf (file, "\tlis %s,", reg_names[12]);
assemble_name (file, buf);
fputs ("@ha\n", file);
asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
asm_fprintf (file, "\tstw %s,4(%s)\n",
reg_names[0], reg_names[1]);
asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
asm_fprintf (file, "\tla %s,", reg_names[0]);
assemble_name (file, buf);
asm_fprintf (file, "@l(%s)\n", reg_names[12]);
}

4
gcc/config/rs6000/rs6000.h
View File

@ -348,10 +348,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define PROCESSOR_DEFAULT PROCESSOR_PPC603
#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
/* Specify the dialect of assembler to use. New mnemonics is dialect one
and the old mnemonics are dialect zero. */
#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
/* Debug support */
#define MASK_DEBUG_STACK 0x01 /* debug stack applications */
#define MASK_DEBUG_ARG 0x02 /* debug argument handling */

606
gcc/config/rs6000/rs6000.md
View File

File diff suppressed because it is too large Load Diff

8
gcc/config/rs6000/rs6000.opt
View File

@ -150,14 +150,6 @@ mstring
Target Report Mask(STRING) Save
Generate string instructions for block moves
mnew-mnemonics
Target Report RejectNegative Mask(NEW_MNEMONICS)
Use new mnemonics for PowerPC architecture
mold-mnemonics
Target Report RejectNegative InverseMask(NEW_MNEMONICS)
Use old mnemonics for PowerPC architecture
msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT)
Do not use hardware floating point

26
gcc/config/rs6000/spe.md
View File

@ -2289,9 +2289,9 @@
known to be dead. */
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands[1], 0))
return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
return \"lwz %L0,%L1\;lwz %0,%1\";
else
return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
return \"lwz%U1%X1 %0,%1\;lwz %L0,%L1\";
}
}"
[(set_attr "length" "8,8")])
@ -2315,9 +2315,9 @@
return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\";
if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
operands[1], 0))
return \"{l|lwz} %Z0,%L1\;{l|lwz} %Y0,%1\";
return \"lwz %Z0,%L1\;lwz %Y0,%1\";
else
return \"{l%U1%X1|lwz%U1%X1} %Y0,%1\;{l|lwz} %Z0,%L1\";
return \"lwz%U1%X1 %Y0,%1\;lwz %Z0,%L1\";
}
}"
[(set_attr "length" "8,8")])
@ -2336,7 +2336,7 @@
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
evmergelo %0,%1,%0
evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0"
evmergelohi %0,%0,%0\;lwz%U1%X1 %0,%1\;evmergelohi %0,%0,%0"
[(set_attr "length" "4,12")])
(define_insn_and_split "*mov_si<mode>_e500_subreg0_elf_low"
@ -2366,7 +2366,7 @@
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
evmergehi %0,%0,%1
evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0"
evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0"
[(set_attr "length" "4,8")])
(define_insn "*mov_si<mode>_e500_subreg4"
@ -2376,7 +2376,7 @@
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1")
lwz%U1%X1 %0,%1")
(define_insn "*mov_si<mode>_e500_subreg4_elf_low"
[(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r") 4)
@ -2385,7 +2385,7 @@
"((TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode))
&& TARGET_ELF && !TARGET_64BIT"
"{ai|addic} %0,%1,%K2")
"addic %0,%1,%K2")
(define_insn "*mov_si<mode>_e500_subreg4_2"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
@ -2394,7 +2394,7 @@
|| (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
"@
mr %0,%1
{st%U0%X0|stw%U0%X0} %1,%0")
stw%U0%X0 %1,%0")
(define_insn "*mov_sitf_e500_subreg8"
[(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
@ -2402,7 +2402,7 @@
"TARGET_E500_DOUBLE"
"@
evmergelo %L0,%1,%L0
evmergelohi %L0,%L0,%L0\;{l%U1%X1|lwz%U1%X1} %L0,%1\;evmergelohi %L0,%L0,%L0"
evmergelohi %L0,%L0,%L0\;lwz%U1%X1 %L0,%1\;evmergelohi %L0,%L0,%L0"
[(set_attr "length" "4,12")])
(define_insn "*mov_sitf_e500_subreg8_2"
@ -2411,7 +2411,7 @@
"TARGET_E500_DOUBLE"
"@
evmergehi %0,%0,%L1
evmergelohi %L1,%L1,%L1\;{st%U0%X0|stw%U0%X0} %L1,%0"
evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0"
[(set_attr "length" "4,8")])
(define_insn "*mov_sitf_e500_subreg12"
@ -2420,7 +2420,7 @@
"TARGET_E500_DOUBLE"
"@
mr %L0,%1
{l%U1%X1|lwz%U1%X1} %L0,%1")
lwz%U1%X1 %L0,%1")
(define_insn "*mov_sitf_e500_subreg12_2"
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
@ -2428,7 +2428,7 @@
"TARGET_E500_DOUBLE"
"@
mr %0,%L1
{st%U0%X0|stw%U0%X0} %L1,%0")
stw%U0%X0 %L1,%0")
;; FIXME: Allow r=CONST0.
(define_insn "*movdf_e500_double"

4
gcc/config/rs6000/sync.md
View File

@ -65,7 +65,7 @@
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
""
"{dcs|sync}"
"sync"
[(set_attr "type" "sync")])
(define_expand "lwsync"
@ -95,7 +95,7 @@
(define_insn "isync"
[(unspec_volatile:BLK [(const_int 0)] UNSPECV_ISYNC)]
""
"{ics|isync}"
"isync"
[(set_attr "type" "isync")])
;; The control dependency used for load dependency described

6
gcc/config/rs6000/sysv4.h
View File

@ -220,7 +220,7 @@ do { \
/* Override rs6000.h definition. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_NEW_MNEMONICS
#define TARGET_DEFAULT 0
/* Override rs6000.h definition. */
#undef PROCESSOR_DEFAULT
@ -450,7 +450,7 @@ do { \
do { \
if (DEFAULT_ABI == ABI_V4) \
asm_fprintf (FILE, \
"\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n", \
"\tstwu %s,-16(%s)\n\tstw %s,12(%s)\n", \
reg_names[1], reg_names[1], reg_names[REGNO], \
reg_names[1]); \
} while (0)
@ -462,7 +462,7 @@ do { \
do { \
if (DEFAULT_ABI == ABI_V4) \
asm_fprintf (FILE, \
"\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n", \
"\tlwz %s,12(%s)\n\taddic %s,%s,16\n", \
reg_names[REGNO], reg_names[1], reg_names[1], \
reg_names[1]); \
} while (0)

2
gcc/config/rs6000/sysv4le.h
View File

@ -20,7 +20,7 @@
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN)
#define TARGET_DEFAULT MASK_LITTLE_ENDIAN
#undef CC1_ENDIAN_DEFAULT_SPEC
#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)"

8
gcc/config/rs6000/vsx.md
View File

@ -545,7 +545,7 @@
xsmaddmdp %x0,%x1,%x3
xsmaddadp %x0,%x1,%x2
xsmaddmdp %x0,%x1,%x3
{fma|fmadd} %0,%1,%2,%3"
fmadd %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
@ -591,7 +591,7 @@
xsmsubmdp %x0,%x1,%x3
xsmsubadp %x0,%x1,%x2
xsmsubmdp %x0,%x1,%x3
{fms|fmsub} %0,%1,%2,%3"
fmsub %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
@ -623,7 +623,7 @@
xsnmaddmdp %x0,%x1,%x3
xsnmaddadp %x0,%x1,%x2
xsnmaddmdp %x0,%x1,%x3
{fnma|fnmadd} %0,%1,%2,%3"
fnmadd %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])
@ -657,7 +657,7 @@
xsnmsubmdp %x0,%x1,%x3
xsnmsubadp %x0,%x1,%x2
xsnmsubmdp %x0,%x1,%x3
{fnms|fnmsub} %0,%1,%2,%3"
fnmsub %0,%1,%2,%3"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_maddsub_d")])

2
gcc/config/rs6000/vxworks.h
View File

@ -98,7 +98,7 @@ VXWORKS_ADDITIONAL_CPP_SPEC
#undef MULTILIB_DEFAULTS
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_NEW_MNEMONICS | MASK_EABI | MASK_STRICT_ALIGN)
#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN)
#undef PROCESSOR_DEFAULT
#define PROCESSOR_DEFAULT PROCESSOR_PPC604

28
gcc/doc/invoke.texi
View File

@ -804,7 +804,6 @@ See RS/6000 and PowerPC Options.
-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol
-mfprnd -mno-fprnd @gol
-mcmpb -mno-cmpb -mmfpgpr -mno-mfpgpr -mhard-dfp -mno-hard-dfp @gol
-mnew-mnemonics -mold-mnemonics @gol
-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
-malign-power -malign-natural @gol
@ -16640,26 +16639,9 @@ The @option{-mpowerpc64} option allows GCC to generate the additional
and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
@option{-mno-powerpc64}.
@item -mnew-mnemonics
@itemx -mold-mnemonics
@opindex mnew-mnemonics
@opindex mold-mnemonics
Select which mnemonics to use in the generated assembler code. With
@option{-mnew-mnemonics}, GCC uses the assembler mnemonics defined for
the PowerPC architecture. With @option{-mold-mnemonics} it uses the
assembler mnemonics defined for the POWER architecture. Instructions
defined in only one architecture have only one mnemonic; GCC uses that
mnemonic irrespective of which of these options is specified.
GCC defaults to the mnemonics appropriate for the architecture in
use. Specifying @option{-mcpu=@var{cpu_type}} sometimes overrides the
value of these option. Unless you are building a cross-compiler, you
should normally not specify either @option{-mnew-mnemonics} or
@option{-mold-mnemonics}, but should instead accept the default.
@item -mcpu=@var{cpu_type}
@opindex mcpu
Set architecture type, register usage, choice of mnemonics, and
Set architecture type, register usage, and
instruction scheduling parameters for machine type @var{cpu_type}.
Supported values for @var{cpu_type} are @samp{401}, @samp{403},
@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp},
@ -16686,7 +16668,7 @@ The @option{-mcpu} options automatically enable or disable the
following options:
@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
-mnew-mnemonics -mpopcntb -mpopcntd -mpowerpc64 @gol
-mpopcntb -mpopcntd -mpowerpc64 @gol
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx}
@ -16706,11 +16688,11 @@ environment.
@item -mtune=@var{cpu_type}
@opindex mtune
Set the instruction scheduling parameters for machine type
@var{cpu_type}, but do not set the architecture type, register usage, or
choice of mnemonics, as @option{-mcpu=@var{cpu_type}} does. The same
@var{cpu_type}, but do not set the architecture type or register usage,
as @option{-mcpu=@var{cpu_type}} does. The same
values for @var{cpu_type} are used for @option{-mtune} as for
@option{-mcpu}. If both are specified, the code generated uses the
architecture, registers, and mnemonics set by @option{-mcpu}, but the
architecture and registers set by @option{-mcpu}, but the
scheduling parameters set by @option{-mtune}.
@item -mcmodel=small

4
libgcc/ChangeLog
View File

@ -1,3 +1,7 @@
2012-08-15 Segher Boessenkool <segher@kernel.crashing.org>
* longlong.h: (whole file, powerpc): Adjust to single assembler syntax.
2012-08-03 H.J. Lu <hongjiu.lu@intel.com>
PR driver/54171

34
libgcc/longlong.h
View File

@ -862,37 +862,37 @@ UDItype __umulsidi3 (USItype, USItype);
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
__asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
__asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
__asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
__asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
#define count_leading_zeros(count, x) \
__asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
__asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 32
#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
|| defined (__ppc__) \
@ -931,32 +931,32 @@ UDItype __umulsidi3 (USItype, USItype);
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
__asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
__asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
__asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
__asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
__asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)