Add GCC support to ENQCMD.

gcc/ChangeLog 2019-01-23 Xuepeng Guo <xuepeng.guo@intel.com> * common/config/i386/i386-common.c (OPTION_MASK_ISA_ENQCMD_SET, OPTION_MASK_ISA_ENQCMD_UNSET): New macros. (ix86_handle_option): Handle -menqcmd. * config.gcc (enqcmdintrin.h): New header file. * config/i386/cpuid.h (bit_ENQCMD): New bit. * config/i386/driver-i386.c (host_detect_local_cpu): Handle -menqcmd. * config/i386/i386-builtin-types.def ((INT, PVOID, PCVOID)): New function type. * config/i386/i386-builtin.def (__builtin_ia32_enqcmd, __builtin_ia32_enqcmds): New builtins. * config/i386/i386-c.c (__ENQCMD__): New macro. * config/i386/i386-option.c (ix86_target_string): Add -menqcmd. (ix86_valid_target_attribute_inner_p): Likewise. * config/i386/i386-expand.c (ix86_expand_builtin): Expand IX86_BUILTIN_ENQCMD and IX86_BUILTIN_ENQCMDS. * config/i386/i386.h (TARGET_ENQCMD): New. * config/i386/i386.md (UNSPECV_ENQCMD, UNSPECV_ENQCMDS): New. (@enqcmd<enqcmd_sfx>_<mode>): New insn pattern. (movdir64b_<mode>): Parameterize to enable share expansion code with ENQCMD in function ix86_expand_builtin. * config/i386/i386.opt: Add -menqcmd. * config/i386/immintrin.h: Include enqcmdintrin.h. * config/i386/enqcmdintrin.h: New intrinsic file. * doc/invoke.texi: Add -menqcmd. gcc/testsuite/ChangeLog 2019-01-23 Xuepeng Guo <xuepeng.guo@intel.com> * gcc.target/i386/enqcmd.c: New test. * gcc.target/i386/enqcmds.c: Likewise. * g++.dg/other/i386-2.C: Add -menqcmd. * g++.dg/other/i386-3.C: Likewise. * gcc.target/i386/sse-12.c: Likewise. * gcc.target/i386/sse-13.c: Likewise. * gcc.target/i386/sse-14.c: Likewise. * gcc.target/i386/sse-23.c: Likewise. From-SVN: r271678
2025-04-10 03:20:27 +08:00 · 2019-05-28 02:45:34 +00:00 · 2019-05-28 02:45:34 +00:00 · 6a10fedad0
commit 6a10fedad0
parent cd8eca2caf
25 changed files with 230 additions and 19 deletions
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@ -7540,6 +7540,37 @@ Fix test-suite.
 	* tree-ssa-dom.c (test_for_singularity): Fix a comment typo.
 	* vr-values.c (find_case_label_ranges): Fix a comment typo.

+2019-01-23  Xuepeng Guo  <xuepeng.guo@intel.com>
+
+	* common/config/i386/i386-common.c
+	(OPTION_MASK_ISA_ENQCMD_SET,
+	OPTION_MASK_ISA_ENQCMD_UNSET): New macros.
+	(ix86_handle_option): Handle -menqcmd.
+	* config.gcc (enqcmdintrin.h): New header file.
+	* config/i386/cpuid.h (bit_ENQCMD): New bit.
+	* config/i386/driver-i386.c (host_detect_local_cpu): Handle
+	-menqcmd.
+	* config/i386/i386-builtin-types.def ((INT, PVOID, PCVOID)): New
+	function type.
+	* config/i386/i386-builtin.def (__builtin_ia32_enqcmd,
+	__builtin_ia32_enqcmds): New builtins.
+	* config/i386/i386-c.c (__ENQCMD__): New macro.
+	* config/i386/i386-option.c (ix86_target_string): Add
+	-menqcmd.
+	(ix86_valid_target_attribute_inner_p): Likewise.
+	* config/i386/i386-expand.c
+	(ix86_expand_builtin): Expand IX86_BUILTIN_ENQCMD and
+	IX86_BUILTIN_ENQCMDS.
+	* config/i386/i386.h (TARGET_ENQCMD): New.
+	* config/i386/i386.md (UNSPECV_ENQCMD, UNSPECV_ENQCMDS): New.
+	(@enqcmd<enqcmd_sfx>_<mode>): New insn pattern.
+	(movdir64b_<mode>): Parameterize to enable share expansion code
+	with ENQCMD in function ix86_expand_builtin.
+	* config/i386/i386.opt: Add -menqcmd.
+	* config/i386/immintrin.h: Include enqcmdintrin.h.
+	* config/i386/enqcmdintrin.h: New intrinsic file.
+	* doc/invoke.texi: Add -menqcmd.
+
 2019-01-23  Bin Cheng  <bin.cheng@arm.com>
 	    Steve Ellcey <sellcey@marvell.com>

--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@ -156,6 +156,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
 #define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE
+#define OPTION_MASK_ISA_ENQCMD_SET OPTION_MASK_ISA_ENQCMD

 /* Define a set of ISAs which aren't available when a given ISA is
   disabled.  MMX and SSE ISAs are handled separately.  */
@ -238,6 +239,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
+#define OPTION_MASK_ISA_ENQCMD_UNSET OPTION_MASK_ISA_ENQCMD

 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
   as -mno-sse4.1. */
@ -659,6 +661,19 @@ ix86_handle_option (struct gcc_options *opts,
 	}
      return true;

+    case OPT_menqcmd:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_ENQCMD_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_ENQCMD_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_ENQCMD_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_ENQCMD_UNSET;
+	}
+      return true;
+
    case OPT_mavx5124fmaps:
      if (value)
 	{
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@ -407,7 +407,8 @@ i[34567]86-*-*)
 		       avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h
 		       avx512vpopcntdqvlintrin.h avx512bitalgintrin.h
 		       pconfigintrin.h wbnoinvdintrin.h movdirintrin.h
-		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h"
+		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h
+		       enqcmdintrin.h"
 	;;
 x86_64-*-*)
 	cpu_type=i386
@ -439,7 +440,8 @@ x86_64-*-*)
 		       avx512vnnivlintrin.h vaesintrin.h vpclmulqdqintrin.h
 		       avx512vpopcntdqvlintrin.h avx512bitalgintrin.h
 		       pconfigintrin.h wbnoinvdintrin.h movdirintrin.h
-		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h"
+		       waitpkgintrin.h cldemoteintrin.h avx512bf16vlintrin.h avx512bf16intrin.h
+		       enqcmdintrin.h"
 	;;
 ia64-*-*)
 	extra_headers=ia64intrin.h
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@ -113,6 +113,7 @@
 #define bit_RDPID	(1 << 22)
 #define bit_MOVDIRI	(1 << 27)
 #define bit_MOVDIR64B	(1 << 28)
+#define bit_ENQCMD	(1 << 29)
 #define bit_CLDEMOTE	(1 << 25)

 /* %edx */
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@ -424,6 +424,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
  unsigned int has_avx512vnni = 0, has_vaes = 0;
  unsigned int has_vpclmulqdq = 0;
  unsigned int has_movdiri = 0, has_movdir64b = 0;
+  unsigned int has_enqcmd = 0;
  unsigned int has_waitpkg = 0;
  unsigned int has_cldemote = 0;
  unsigned int has_avx512bf16 = 0;
@ -526,6 +527,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
      has_avx512bitalg = ecx & bit_AVX512BITALG;
      has_movdiri = ecx & bit_MOVDIRI;
      has_movdir64b = ecx & bit_MOVDIR64B;
+      has_enqcmd = ecx & bit_ENQCMD;
      has_cldemote = ecx & bit_CLDEMOTE;

      has_avx5124vnniw = edx & bit_AVX5124VNNIW;
@ -1144,6 +1146,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
      const char *avx512bitalg = has_avx512bitalg ? " -mavx512bitalg" : " -mno-avx512bitalg";
      const char *movdiri = has_movdiri ? " -mmovdiri" : " -mno-movdiri";
      const char *movdir64b = has_movdir64b ? " -mmovdir64b" : " -mno-movdir64b";
+      const char *enqcmd = has_enqcmd ? " -menqcmd" : " -mno-enqcmd";
      const char *waitpkg = has_waitpkg ? " -mwaitpkg" : " -mno-waitpkg";
      const char *cldemote = has_cldemote ? " -mcldemote" : " -mno-cldemote";
      const char *ptwrite = has_ptwrite ? " -mptwrite" : " -mno-ptwrite";
@ -1162,7 +1165,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
 			clwb, mwaitx, clzero, pku, rdpid, gfni, shstk,
 			avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
 			avx512bitalg, movdiri, movdir64b, waitpkg, cldemote,
-			ptwrite, avx512bf16,
+			ptwrite, avx512bf16, enqcmd,
 			NULL);
    }

--- a/gcc/config/i386/enqcmdintrin.h
+++ b/gcc/config/i386/enqcmdintrin.h
@ -0,0 +1,55 @@
+/* Copyright (C) 2019 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+# error "Never use <enqcmdntrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef _ENQCMDNTRIN_H_INCLUDED
+#define _ENQCMDNTRIN_H_INCLUDED
+
+#ifndef __ENQCMD__
+#pragma GCC push_options
+#pragma GCC target ("enqcmd")
+#define __DISABLE_ENQCMD__
+#endif /* __ENQCMD__ */
+
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_enqcmd (void * __P, const void * __Q)
+{
+  return __builtin_ia32_enqcmd (__P, __Q);
+}
+
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_enqcmds (void * __P, const void * __Q)
+{
+  return __builtin_ia32_enqcmds (__P, __Q);
+}
+
+#ifdef __DISABLE_ENQCMD__
+#undef __DISABLE_ENQCMD__
+#pragma GCC pop_options
+#endif /* __DISABLE_ENQCMD__ */
+#endif /* _ENQCMDNTRIN_H_INCLUDED.  */
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@ -533,6 +533,7 @@ DEF_FUNCTION_TYPE (VOID, PFLOAT, V16SF)
 DEF_FUNCTION_TYPE (VOID, PINT, INT)
 DEF_FUNCTION_TYPE (VOID, PUNSIGNED, UNSIGNED)
 DEF_FUNCTION_TYPE (VOID, PVOID, PCVOID)
+DEF_FUNCTION_TYPE (INT, PVOID, PCVOID)
 DEF_FUNCTION_TYPE (VOID, PLONGLONG, LONGLONG)
 DEF_FUNCTION_TYPE (VOID, PULONGLONG, ULONGLONG)
 DEF_FUNCTION_TYPE (VOID, PV2SI, V2SI)
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@ -434,6 +434,10 @@ BDESC (0, OPTION_MASK_ISA_MOVDIR64B, CODE_FOR_nothing, "__builtin_ia32_movdir64b
 BDESC (0, OPTION_MASK_ISA_PTWRITE, CODE_FOR_ptwritesi, "__builtin_ia32_ptwrite32", IX86_BUILTIN_PTWRITE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED)
 BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA_PTWRITE, CODE_FOR_ptwritedi, "__builtin_ia32_ptwrite64", IX86_BUILTIN_PTWRITE64, UNKNOWN, (int) VOID_FTYPE_UINT64)

+/* ENQCMD */
+BDESC (0, OPTION_MASK_ISA_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmd", IX86_BUILTIN_ENQCMD, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID)
+BDESC (0, OPTION_MASK_ISA_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmds", IX86_BUILTIN_ENQCMDS, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID)
+
 BDESC_END (SPECIAL_ARGS, ARGS)

 /* Builtins with variable number of arguments.  */
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@ -552,6 +552,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
    def_or_undef (parse_in, "__AVX512BF16__");
  if (TARGET_MMX_WITH_SSE)
    def_or_undef (parse_in, "__MMX_WITH_SSE__");
+  if (isa_flag2 & OPTION_MASK_ISA_ENQCMD)
+    def_or_undef (parse_in, "__ENQCMD__");
  if (TARGET_IAMCU)
    {
      def_or_undef (parse_in, "__iamcu");
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@ -11313,6 +11313,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
      emit_move_insn (target, op0);
      return target;

+    case IX86_BUILTIN_ENQCMD:
+    case IX86_BUILTIN_ENQCMDS:
    case IX86_BUILTIN_MOVDIR64B:

      arg0 = CALL_EXPR_ARG (exp, 0);
@ -11328,11 +11330,33 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
      }
      op1 = gen_rtx_MEM (XImode, op1);

-      insn = (TARGET_64BIT
-		? gen_movdir64b_di (op0, op1)
-		: gen_movdir64b_si (op0, op1));
-      emit_insn (insn);
-      return 0;
+      if (fcode == IX86_BUILTIN_MOVDIR64B)
+	{
+	  emit_insn (gen_movdir64b (Pmode, op0, op1));
+	  return 0;
+	}
+      else
+	{
+	  rtx pat;
+
+	  target = gen_reg_rtx (SImode);
+	  emit_move_insn (target, const0_rtx);
+	  target = gen_rtx_SUBREG (QImode, target, 0);
+
+	  if (fcode == IX86_BUILTIN_ENQCMD)
+	    pat = gen_enqcmd (UNSPECV_ENQCMD, Pmode, op0, op1);
+	  else
+	    pat = gen_enqcmd (UNSPECV_ENQCMDS, Pmode, op0, op1);
+
+	  emit_insn (pat);
+
+	  emit_insn (gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode, target),
+				  gen_rtx_fmt_ee (EQ, QImode,
+						  SET_DEST (pat),
+						  const0_rtx)));
+
+	  return SUBREG_REG (target);
+	}

    case IX86_BUILTIN_FXSAVE:
    case IX86_BUILTIN_FXRSTOR:
--- a/gcc/config/i386/i386-options.c
+++ b/gcc/config/i386/i386-options.c
@ -210,7 +210,8 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
    { "-mwaitpkg",	OPTION_MASK_ISA_WAITPKG },
    { "-mcldemote",	OPTION_MASK_ISA_CLDEMOTE },
    { "-mptwrite",	OPTION_MASK_ISA_PTWRITE },
-    { "-mavx512bf16",	OPTION_MASK_ISA_AVX512BF16 }
+    { "-mavx512bf16",	OPTION_MASK_ISA_AVX512BF16 },
+    { "-menqcmd",       OPTION_MASK_ISA_ENQCMD }
  };
  static struct ix86_target_opts isa_opts[] =
  {
@ -921,6 +922,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
    IX86_ATTR_ISA ("cldemote", OPT_mcldemote),
    IX86_ATTR_ISA ("ptwrite",   OPT_mptwrite),
    IX86_ATTR_ISA ("avx512bf16",   OPT_mavx512bf16),
+    IX86_ATTR_ISA ("enqcmd", OPT_menqcmd),

    /* enum options */
    IX86_ATTR_ENUM ("fpmath=",	OPT_mfpmath_),
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@ -195,6 +195,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_PTWRITE_P(x)	TARGET_ISA_PTWRITE_P(x)
 #define TARGET_AVX512BF16	TARGET_ISA_AVX512BF16
 #define TARGET_AVX512BF16_P(x)	TARGET_ISA_AVX512BF16_P(x)
+#define TARGET_ENQCMD	TARGET_ISA_ENQCMD
+#define TARGET_ENQCMD_P(x) TARGET_ISA_ENQCMD_P(x)

 #define TARGET_LP64	TARGET_ABI_64
 #define TARGET_LP64_P(x)	TARGET_ABI_64_P(x)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@ -295,6 +295,10 @@
  UNSPECV_SPECULATION_BARRIER

  UNSPECV_PTWRITE
+
+  ;; For ENQCMD and ENQCMDS support
+  UNSPECV_ENQCMD
+  UNSPECV_ENQCMDS
 ])

 ;; Constants to represent rounding modes in the ROUND instruction
@ -20318,7 +20322,7 @@
  "movdiri\t{%1, %0|%0, %1}"
  [(set_attr "type" "other")])

-(define_insn "movdir64b_<mode>"
+(define_insn "@movdir64b_<mode>"
  [(unspec_volatile:XI [(match_operand:P 0 "register_operand" "r")
 			(match_operand:XI 1 "memory_operand")]
 		       UNSPECV_MOVDIR64B)]
@ -20326,6 +20330,20 @@
  "movdir64b\t{%1, %0|%0, %1}"
  [(set_attr "type" "other")])

+;; ENQCMD and ENQCMDS
+
+(define_int_iterator ENQCMD [UNSPECV_ENQCMD UNSPECV_ENQCMDS])
+(define_int_attr enqcmd_sfx [(UNSPECV_ENQCMD "") (UNSPECV_ENQCMDS "s")])
+
+(define_insn "@enqcmd<enqcmd_sfx>_<mode>"
+  [(set (reg:CCZ FLAGS_REG)
+	(unspec_volatile:CCZ [(match_operand:P 0 "register_operand" "r")
+			      (match_operand:XI 1 "memory_operand" "m")]
+			     ENQCMD))]
+  "TARGET_ENQCMD"
+  "enqcmd<enqcmd_sfx>\t{%1, %0|%0, %1}"
+  [(set_attr "type" "other")])
+
 ;; WAITPKG

 (define_insn "umwait"
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@ -1106,3 +1106,7 @@ mavx512bf16
 Target Report Mask(ISA_AVX512BF16) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
 AVX512BF16 built-in functions and code generation.
+
+menqcmd
+Target Report Mask(ISA_ENQCMD) Var(ix86_isa_flags2) Save
+Support ENQCMD built-in functions and code generation.
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@ -134,6 +134,8 @@

 #include <avx512bf16intrin.h>

+#include <enqcmdintrin.h>
+
 #include <rdseedintrin.h>

 #include <prfchwintrin.h>
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@ -1274,7 +1274,7 @@ See RS/6000 and PowerPC Options.
 -msse4a  -m3dnow  -m3dnowa  -mpopcnt  -mabm  -mbmi  -mtbm  -mfma4  -mxop @gol
 -madx  -mlzcnt  -mbmi2  -mfxsr  -mxsave  -mxsaveopt  -mrtm  -mhle  -mlwp @gol
 -mmwaitx  -mclzero  -mpku  -mthreads  -mgfni  -mvaes  -mwaitpkg @gol
-mshstk -mmanual-endbr -mforce-indirect-call -mavx512vbmi2 -mavx512bf16 @gol
+-mshstk -mmanual-endbr -mforce-indirect-call  -mavx512vbmi2 -mavx512bf16 -menqcmd @gol
 -mvpclmulqdq  -mavx512bitalg  -mmovdiri  -mmovdir64b  -mavx512vpopcntdq @gol
 -mavx5124fmaps  -mavx512vnni  -mavx5124vnniw  -mprfchw  -mrdpid @gol
 -mrdseed  -msgx @gol
@ -28095,6 +28095,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@itemx -mmovdir64b
@opindex mmovdir64b
@need 200
+@itemx -menqcmd
+@opindex menqcmd
+@need 200
@itemx -mavx512vpopcntdq
@opindex mavx512vpopcntdq
@need 200
@ -28116,8 +28119,8 @@ AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
 WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,
 3DNow!@:, enhanced 3DNow!@:, POPCNT, ABM, ADX, BMI, BMI2, LZCNT, FXSR, XSAVE,
 XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2,
-GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16
-AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, or CLDEMOTE
+GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
+ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, or CLDEMOTE
 extended instruction sets.  Each has a corresponding @option{-mno-} option to
 disable use of these instructions.

--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@ -4560,6 +4560,17 @@
 	PR target/89290
 	* gcc.target/i386/pr89290.c: New test.

+2019-01-23  Xuepeng Guo  <xuepeng.guo@intel.com>
+
+	* gcc.target/i386/enqcmd.c: New test.
+	* gcc.target/i386/enqcmds.c: Likewise.
+	* g++.dg/other/i386-2.C: Add -menqcmd.
+	* g++.dg/other/i386-3.C: Likewise.
+	* gcc.target/i386/sse-12.c: Likewise.
+	* gcc.target/i386/sse-13.c: Likewise.
+	* gcc.target/i386/sse-14.c: Likewise.
+	* gcc.target/i386/sse-23.c: Likewise.
+
 2019-01-23  Xiong Hu Luo  <luoxhu@linux.vnet.ibm.com>

 	* gcc.target/powerpc/crypto-builtin-1.c
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt  -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt  -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd" } */

 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
   xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd" } */

 /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
   xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
--- a/gcc/testsuite/gcc.target/i386/enqcmd.c
+++ b/gcc/testsuite/gcc.target/i386/enqcmd.c
@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-menqcmd -O2" } */
+/* { dg-final { scan-assembler-times "\tenqcmd" 1 } } */
+/* { dg-final { scan-assembler-times "\tsete" 1 } } */
+
+#include <x86intrin.h>
+
+unsigned int w;
+unsigned int array[16];
+
+int
+test_enqcmd (void)
+{
+  return _enqcmd(&w, array);
+}
+
--- a/gcc/testsuite/gcc.target/i386/enqcmds.c
+++ b/gcc/testsuite/gcc.target/i386/enqcmds.c
@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-menqcmd -O2" } */
+/* { dg-final { scan-assembler-times "\tenqcmds" 1 } } */
+/* { dg-final { scan-assembler-times "\tsete" 1 } } */
+
+#include <x86intrin.h>
+
+unsigned int w;
+unsigned int array[16];
+int
+test_enqcmds (void)
+{
+  return _enqcmds(&w, array);
+}
+
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@ -3,7 +3,7 @@
   popcntintrin.h gfniintrin.h and mm_malloc.h are usable
   with -O -std=c89 -pedantic-errors.  */
 /* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd" } */

 #include <x86intrin.h>

--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd" } */
 /* { dg-add-options bind_pic_locally } */

 #include <mm_malloc.h>
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd" } */
 /* { dg-add-options bind_pic_locally } */

 #include <mm_malloc.h>
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@ -696,6 +696,6 @@
 #define __builtin_ia32_vpclmulqdq_v2di(A, B, C)  __builtin_ia32_vpclmulqdq_v2di(A, B, 1) 
 #define __builtin_ia32_vpclmulqdq_v8di(A, B, C)  __builtin_ia32_vpclmulqdq_v8di(A, B, 1) 

-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd")

 #include <x86intrin.h>