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alpha.c (alpha_handle_trap_shadows): Remove do-nothing exit.
* alpha.c (alpha_handle_trap_shadows): Remove do-nothing exit.
Tag trapb and next insn with TImode.
(alphaev5_insn_pipe, alphaev5_next_group, alphaev5_align_insns): New.
(alpha_reorg): Add conditional for alpha_handle_trap_shadows.
Invoke alphaev5_align_insns as appropriate.
* alpha.md (attr type): Add multi.
(define_asm_attributes): New.
(prologue_stack_probe_loop, builtin_setjmp_receiver): Set type multi.
(arg_home): Likewise.
(fnop, unop, realign): New.
From-SVN: r22010
This commit is contained in:
Richard Henderson
Richard Henderson
parent
4bdc8810f6
commit
68aed21b05
@ -1,3 +1,22 @@
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Wed Aug 26 18:38:15 1998 Richard Henderson <rth@cygnus.com>
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* haifa-sched.c (last_clock_var): New.
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(schedule_block): Initialize it.
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(schedule_insn): Use it to fill insn modes with issue information.
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* alpha.c (alpha_handle_trap_shadows): Remove do-nothing exit.
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Tag trapb and next insn with TImode.
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(alphaev5_insn_pipe, alphaev5_next_group, alphaev5_align_insns): New.
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(alpha_reorg): Add conditional for alpha_handle_trap_shadows.
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Invoke alphaev5_align_insns as appropriate.
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* alpha.h (LABEL_ALIGN_AFTER_BARRIER): Was ALIGN_LABEL_AFTER_BARRIER.
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(MD_SCHED_VARIABLE_ISSUE): New.
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* alpha.md (attr type): Add multi.
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(define_asm_attributes): New.
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(prologue_stack_probe_loop, builtin_setjmp_receiver): Set type multi.
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(arg_home): Likewise.
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(fnop, unop, realign): New.
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Wed Aug 26 15:55:41 1998 Jim Wilson <wilson@cygnus.com>
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* iris5.h (PREFERRED_DEBUGGING_TYPE): Undef.
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@ -1416,7 +1416,7 @@ alpha_emit_conditional_move (cmp, mode)
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abort ();
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}
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/* ??? We mark the the branch mode to be CCmode to prevent the compare
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/* ??? We mark the branch mode to be CCmode to prevent the compare
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and cmov from being combined, since the compare insn follows IEEE
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rules that the cmov does not. */
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if (alpha_compare_fp_p && !flag_fast_math)
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@ -4090,10 +4090,7 @@ alpha_handle_trap_shadows (insns)
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{
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struct shadow_summary shadow;
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int trap_pending, exception_nesting;
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rtx i;
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if (alpha_tp == ALPHA_TP_PROG && !flag_exceptions)
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return;
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rtx i, n;
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trap_pending = 0;
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exception_nesting = 0;
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@ -4196,7 +4193,9 @@ alpha_handle_trap_shadows (insns)
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else
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{
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close_shadow:
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emit_insn_before (gen_trapb (), i);
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n = emit_insn_before (gen_trapb (), i);
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PUT_MODE (n, TImode);
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PUT_MODE (i, TImode);
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trap_pending = 0;
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shadow.used.i = 0;
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shadow.used.fp = 0;
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@ -4218,14 +4217,344 @@ alpha_handle_trap_shadows (insns)
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}
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}
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}
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#ifdef HAIFA
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/* Alpha can only issue instruction groups simultaneously if they are
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suitibly aligned. This is very processor-specific. */
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enum alphaev5_pipe {
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EV5_STOP = 0,
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EV5_NONE = 1,
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EV5_E01 = 2,
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EV5_E0 = 4,
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EV5_E1 = 8,
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EV5_FAM = 16,
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EV5_FA = 32,
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EV5_FM = 64
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};
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static enum alphaev5_pipe
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alphaev5_insn_pipe (insn)
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rtx insn;
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{
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if (recog_memoized (insn) < 0)
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return EV5_STOP;
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if (get_attr_length (insn) != 4)
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return EV5_STOP;
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switch (get_attr_type (insn))
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{
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case TYPE_ILD:
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case TYPE_FLD:
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case TYPE_LDSYM:
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case TYPE_IADD:
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case TYPE_ILOG:
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case TYPE_ICMOV:
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case TYPE_ICMP:
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return EV5_E01;
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case TYPE_IST:
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case TYPE_FST:
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case TYPE_SHIFT:
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case TYPE_IMUL:
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case TYPE_MISC:
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case TYPE_MVI:
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return EV5_E0;
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case TYPE_IBR:
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case TYPE_JSR:
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return EV5_E1;
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case TYPE_FCPYS:
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return EV5_FAM;
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case TYPE_FBR:
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case TYPE_FCMOV:
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case TYPE_FADD:
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case TYPE_FDIV:
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return EV5_FA;
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case TYPE_FMUL:
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return EV5_FM;
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}
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abort();
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}
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/* IN_USE is a mask of the slots currently filled within the
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insn group. The mask bits come from alphaev5_pipe above.
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If EV5_E01 is set, then the insn in EV5_E0 can be swapp
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by the hardware into EV5_E1.
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LEN is, of course, the length of the group in bytes. */
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static rtx
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alphaev5_next_group (insn, pin_use, plen)
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rtx insn;
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int *pin_use, *plen;
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{
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int len, in_use;
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len = in_use = 0;
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if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
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goto next;
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do
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{
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enum alphaev5_pipe pipe;
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rtx prev;
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pipe = alphaev5_insn_pipe (insn);
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switch (pipe)
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{
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case EV5_STOP:
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/* Force complex instructions to start new groups. */
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if (in_use)
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goto done;
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/* If this is a completely unrecognized insn, its an asm.
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We don't know how long it is, so record length as -1 to
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signal a needed realignment. */
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if (recog_memoized (insn) < 0)
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len = -1;
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else
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len = get_attr_length (insn);
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goto next;
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/* ??? Most of the places below, we would like to abort, as
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it would indicate an error either in Haifa, or in the
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scheduling description. Unfortunately, Haifa never
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schedules the last instruction of the BB, so we don't
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have an accurate TI bit to go off. */
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case EV5_E01:
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if (in_use & EV5_E0)
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{
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if (in_use & EV5_E1)
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goto done;
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in_use |= EV5_E1;
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}
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else
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in_use |= EV5_E0 | EV5_E01;
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break;
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case EV5_E0:
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if (in_use & EV5_E0)
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{
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if (!(in_use & EV5_E01) || in_use & EV5_E1)
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goto done;
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in_use |= EV5_E1;
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}
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in_use |= EV5_E0;
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break;
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case EV5_E1:
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if (in_use & EV5_E1)
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goto done;
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in_use |= EV5_E1;
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break;
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case EV5_FAM:
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if (in_use & EV5_FA)
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{
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if (in_use & EV5_FM)
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goto done;
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in_use |= EV5_FM;
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}
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else
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in_use |= EV5_FA | EV5_FAM;
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break;
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case EV5_FA:
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if (in_use & EV5_FA)
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goto done;
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in_use |= EV5_FA;
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break;
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case EV5_FM:
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if (in_use & EV5_FM)
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goto done;
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in_use |= EV5_FM;
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break;
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case EV5_NONE:
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break;
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default:
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abort();
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}
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len += 4;
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/* Haifa doesn't do well scheduling branches. */
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/* ??? If this is predicted not-taken, slotting continues, except
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that no more IBR, FBR, or JSR insns may be slotted. */
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if (GET_CODE (insn) == JUMP_INSN)
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goto next;
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insn = next_nonnote_insn (insn);
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if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
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goto done;
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/* Let Haifa tell us where it thinks insn group boundaries are. */
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if (GET_MODE (insn) == TImode)
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goto done;
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}
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while (insn);
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done:
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*plen = len;
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*pin_use = in_use;
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return insn;
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next:
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insn = next_nonnote_insn (insn);
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goto done;
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}
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static void
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alphaev5_align_insns (insns)
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rtx insns;
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{
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/* ALIGN is the known alignment for the insn group. */
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int align;
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/* OFS is the offset of the current insn in the insn group. */
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int ofs;
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int prev_in_use, in_use, len;
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rtx i, next;
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/* Let shorten branches care for assigning alignments to code labels. */
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shorten_branches (insns);
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ofs = prev_in_use = 0;
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if (alpha_does_function_need_gp())
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{
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ofs = 8;
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prev_in_use = EV5_E01 | EV5_E0;
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}
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align = (FUNCTION_BOUNDARY/BITS_PER_UNIT < 16
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? FUNCTION_BOUNDARY/BITS_PER_UNIT : 16);
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i = insns;
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if (GET_CODE (i) == NOTE)
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i = next_nonnote_insn (i);
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while (i)
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{
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next = alphaev5_next_group (i, &in_use, &len);
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/* When we see a label, resync alignment etc. */
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if (GET_CODE (i) == CODE_LABEL)
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{
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int new_align = 1 << label_to_alignment (i);
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if (new_align >= align)
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{
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align = new_align < 16 ? new_align : 16;
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ofs = 0;
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}
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else if (ofs & (new_align-1))
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ofs = (ofs | (new_align-1)) + 1;
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if (len != 0)
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abort();
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}
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/* Handle complex instructions special. */
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else if (in_use == 0)
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{
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/* Asms will have length < 0. This is a signal that we have
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lost alignment knowledge. Assume, however, that the asm
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will not mis-align instructions. */
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if (len < 0)
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{
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ofs = 0;
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align = 4;
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len = 0;
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}
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}
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/* If the known alignment is smaller than the recognized insn group,
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realign the output. */
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else if (align < len)
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{
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int new_log_align = len > 8 ? 4 : 3;
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rtx where;
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where = prev_nonnote_insn (i);
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if (!where || GET_CODE (where) != CODE_LABEL)
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where = i;
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emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
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align = 1 << new_log_align;
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ofs = 0;
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}
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/* If the group won't fit in the same INT16 as the previous,
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we need to add padding to keep the group together. Rather
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than simply leaving the insn filling to the assembler, we
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can make use of the knowledge of what sorts of instructions
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were issued in the previous group to make sure that all of
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the added nops are really free. */
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else if (ofs + len > align)
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{
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int nop_count = (align - ofs) / 4;
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rtx where;
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where = prev_nonnote_insn (i);
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if (!where || GET_CODE (where) != CODE_LABEL)
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where = i;
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do
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{
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if (!(prev_in_use & EV5_E1))
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{
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prev_in_use |= EV5_E1;
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emit_insn_before (gen_nop(), where);
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}
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else if (TARGET_FP && !(prev_in_use & EV5_FA))
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{
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prev_in_use |= EV5_FA;
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emit_insn_before (gen_fnop(), where);
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}
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else if (TARGET_FP && !(prev_in_use & EV5_FM))
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{
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prev_in_use |= EV5_FM;
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emit_insn_before (gen_fnop(), where);
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}
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else
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emit_insn_before (gen_unop(), where);
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}
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while (--nop_count);
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ofs = 0;
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}
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ofs = (ofs + len) & (align - 1);
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prev_in_use = in_use;
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i = next;
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}
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}
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#endif /* HAIFA */
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/* Machine dependant reorg pass. */
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void
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alpha_reorg (insns)
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rtx insns;
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{
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alpha_handle_trap_shadows (insns);
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if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
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alpha_handle_trap_shadows (insns);
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#ifdef HAIFA
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/* Due to the number of extra trapb insns, don't bother fixing up
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alignment when trap precision is instruction. Moreover, we can
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only do our job when sched2 is run and Haifa is our scheduler. */
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if (optimize && !optimize_size
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&& alpha_tp != ALPHA_TP_INSN
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&& flag_schedule_insns_after_reload)
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{
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if (alpha_cpu == PROCESSOR_EV5)
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alphaev5_align_insns (insns);
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}
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#endif
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}
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@ -38,6 +38,7 @@
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;; 3 builtin_longjmp
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;; 4 trapb
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;; 5 prologue_stack_probe_loop
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;; 6 realign
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;; Processor type -- this attribute must exactly match the processor_type
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;; enumeration in alpha.h.
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@ -51,9 +52,13 @@
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;; separately.
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(define_attr "type"
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"ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof"
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"ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
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(const_string "iadd"))
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;; Describe a user's asm statement.
|
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(define_asm_attributes
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[(set_attr "type" "multi")])
|
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|
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;; Define the operand size an insn operates on. Used primarily by mul
|
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;; and div operations that have size dependant timings.
|
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@ -3833,12 +3838,6 @@
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"jmp $31,(%0),0"
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[(set_attr "type" "ibr")])
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(define_insn "nop"
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[(const_int 0)]
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""
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"nop"
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[(set_attr "type" "ilog")])
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|
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(define_expand "tablejump"
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[(use (match_operand:SI 0 "register_operand" ""))
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(use (match_operand:SI 1 "" ""))]
|
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@ -5124,7 +5123,8 @@
|
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|
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return \"\";
|
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}"
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[(set_attr "length" "16")])
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[(set_attr "length" "16")
|
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(set_attr "type" "multi")])
|
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|
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(define_expand "prologue"
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[(clobber (const_int 0))]
|
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@ -5171,13 +5171,15 @@
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[(unspec_volatile [(match_operand 0 "" "")] 2)]
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"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
|
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"\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
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[(set_attr "length" "8")])
|
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[(set_attr "length" "8")
|
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(set_attr "type" "multi")])
|
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|
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(define_insn ""
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[(unspec_volatile [(match_operand 0 "" "")] 2)]
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"! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
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"br $27,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($27)"
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[(set_attr "length" "12")])
|
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[(set_attr "length" "12")
|
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(set_attr "type" "multi")])
|
||||
|
||||
(define_expand "nonlocal_goto_receiver"
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[(unspec_volatile [(const_int 0)] 1)
|
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@ -5209,7 +5211,8 @@
|
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(clobber (reg:DI 0))]
|
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"TARGET_OPEN_VMS"
|
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"lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
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[(set_attr "length" "16")])
|
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[(set_attr "length" "16")
|
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(set_attr "type" "multi")])
|
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|
||||
;; Close the trap shadow of preceeding instructions. This is generated
|
||||
;; by alpha_reorg.
|
||||
@ -5219,6 +5222,31 @@
|
||||
""
|
||||
"trapb"
|
||||
[(set_attr "type" "misc")])
|
||||
|
||||
;; No-op instructions used by machine-dependant reorg to preserve
|
||||
;; alignment for instruction issue.
|
||||
|
||||
(define_insn "nop"
|
||||
[(const_int 0)]
|
||||
""
|
||||
"nop"
|
||||
[(set_attr "type" "ilog")])
|
||||
|
||||
(define_insn "fnop"
|
||||
[(const_int 1)]
|
||||
"TARGET_FP"
|
||||
"fnop"
|
||||
[(set_attr "type" "fcpys")])
|
||||
|
||||
(define_insn "unop"
|
||||
[(const_int 2)]
|
||||
""
|
||||
"unop")
|
||||
|
||||
(define_insn "realign"
|
||||
[(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
|
||||
""
|
||||
".align %0 #realign")
|
||||
|
||||
;; Peepholes go at the end.
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user