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re PR rtl-optimization/38034 (Unnecessary register move)

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gcc/

2009-03-27  H.J. Lu  <hongjiu.lu@intel.com>
	    Jakub Jelinek  <jakub@redhat.com>

	PR target/38034
	* config/ia64/sync.md (cmpxchg_rel_<mode>): Replace input
	gr_register_operand with gr_reg_or_0_operand.
	(cmpxchg_rel_di): Likewise.
	(sync_lock_test_and_set<mode>): Likewise.

gcc/testsuite/

2009-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/38034
	* gcc.target/ia64/sync-1.c: New.

Co-Authored-By: Jakub Jelinek <jakub@redhat.com>

From-SVN: r145135
This commit is contained in:
H.J. Lu 2009-03-27 22:28:20 +00:00 committed by H.J. Lu
parent c619e9823e
commit 689b689c17
4 changed files with 43 additions and 6 deletions
gcc
ChangeLog
config/ia64
sync.md
testsuite
ChangeLog
gcc.target/ia64
sync-1.c

9
gcc/ChangeLog

@ -1,3 +1,12 @@
2009-03-27 H.J. Lu <hongjiu.lu@intel.com>
Jakub Jelinek <jakub@redhat.com>
PR target/38034
* config/ia64/sync.md (cmpxchg_rel_<mode>): Replace input
gr_register_operand with gr_reg_or_0_operand.
(cmpxchg_rel_di): Likewise.
(sync_lock_test_and_set<mode>): Likewise.
2009-03-27 H.J. Lu <hongjiu.lu@intel.com>
* jump.c (rtx_renumbered_equal_p): Use subreg_get_info.

12
gcc/config/ia64/sync.md

@ -151,10 +151,10 @@
(unspec:I124MODE
[(match_dup 1)
(match_operand:DI 2 "ar_ccv_reg_operand" "")
(match_operand:I124MODE 3 "gr_register_operand" "r")]
(match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")]
UNSPEC_CMPXCHG_ACQ))]
""
"cmpxchg<modesuffix>.rel %0 = %1, %3, %2"
"cmpxchg<modesuffix>.rel %0 = %1, %r3, %2"
[(set_attr "itanium_class" "sem")])
(define_insn "cmpxchg_rel_di"
@ -163,19 +163,19 @@
(set (match_dup 1)
(unspec:DI [(match_dup 1)
(match_operand:DI 2 "ar_ccv_reg_operand" "")
(match_operand:DI 3 "gr_register_operand" "r")]
(match_operand:DI 3 "gr_reg_or_0_operand" "rO")]
UNSPEC_CMPXCHG_ACQ))]
""
"cmpxchg8.rel %0 = %1, %3, %2"
"cmpxchg8.rel %0 = %1, %r3, %2"
[(set_attr "itanium_class" "sem")])
(define_insn "sync_lock_test_and_set<mode>"
[(set (match_operand:IMODE 0 "gr_register_operand" "=r")
(match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
(set (match_dup 1)
(match_operand:IMODE 2 "gr_register_operand" "r"))]
(match_operand:IMODE 2 "gr_reg_or_0_operand" "rO"))]
""
"xchg<modesuffix> %0 = %1, %2"
"xchg<modesuffix> %0 = %1, %r2"
[(set_attr "itanium_class" "sem")])
(define_expand "sync_lock_release<mode>"

5
gcc/testsuite/ChangeLog

@ -1,3 +1,8 @@
2009-03-27 H.J. Lu <hongjiu.lu@intel.com>
PR target/38034
* gcc.target/ia64/sync-1.c: New.
2009-03-27 H.J. Lu <hongjiu.lu@intel.com>
PR target/39472

23
gcc/testsuite/gcc.target/ia64/sync-1.c Normal file

@ -0,0 +1,23 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler "xchg4 .*, r0" } } */
/* { dg-final { scan-assembler "cmpxchg4.*, r0, .*" } } */
/* { dg-final { scan-assembler "cmpxchg8.*, r0, .*" } } */
int
foo1 (int *p)
{
return __sync_lock_test_and_set (p, 0);
}
int
foo2 (int *p, int v)
{
return __sync_bool_compare_and_swap (p, v, 0);
}
long
foo3 (long *p, long v)
{
return __sync_bool_compare_and_swap (p, v, 0);
}