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RISC-V: Add newline to the end of file [NFC]
gcc/ChangeLog: * config/riscv/riscv-c.cc: Add newline to the end of file. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pragma-1.c: Add newline to the end of file. * gcc.target/riscv/rvv/base/pragma-2.c: Ditto. * gcc.target/riscv/rvv/base/pragma-3.c: Ditto. * gcc.target/riscv/rvv/base/user-1.c: Ditto. * gcc.target/riscv/rvv/base/user-2.c: Ditto. * gcc.target/riscv/rvv/base/user-3.c: Ditto. * gcc.target/riscv/rvv/base/user-4.c: Ditto. * gcc.target/riscv/rvv/base/user-5.c: Ditto. * gcc.target/riscv/rvv/base/user-6.c: Ditto. * gcc.target/riscv/rvv/base/vread_csr.c: Ditto. * gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
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@ -190,4 +190,4 @@ void
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riscv_register_pragmas (void)
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{
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c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic);
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}
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}
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@ -1,4 +1,4 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */
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#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' option 'vector' needs 'V' extension enabled} } */
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#pragma riscv intrinsic "vector" /* { dg-error {#pragma riscv intrinsic' option 'vector' needs 'V' extension enabled} } */
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@ -1,4 +1,4 @@
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/* { dg-do compile } */
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/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
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#pragma riscv intrinsic "vector"
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#pragma riscv intrinsic "vector"
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@ -1,4 +1,4 @@
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/* { dg-do compile } */
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/* { dg-skip-if "test rvv intrinsic" { *-*-* } { "*" } { "-march=rv*v*" } } */
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#pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv intrinsic' option 'report-error'} } */
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#pragma riscv intrinsic "report-error" /* { dg-error {unknown '#pragma riscv intrinsic' option 'report-error'} } */
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@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;}
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void foo62 () {vfloat64m1_t t;}
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void foo63 () {vfloat64m2_t t;}
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void foo64 () {vfloat64m4_t t;}
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void foo65 () {vfloat64m8_t t;}
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void foo65 () {vfloat64m8_t t;}
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@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;} /* { dg-error {unknown type name 'vfloat32m8_t'}
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void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
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void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
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void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;}
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void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
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void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
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void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;}
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void foo62 () {vfloat64m1_t t;}
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void foo63 () {vfloat64m2_t t;}
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void foo64 () {vfloat64m4_t t;}
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void foo65 () {vfloat64m8_t t;}
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void foo65 () {vfloat64m8_t t;}
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@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;} /* { dg-error {unknown type name 'vfloat32m8_t'}
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void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
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void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
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void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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@ -62,4 +62,4 @@ void foo61 () {vfloat32m8_t t;}
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void foo62 () {vfloat64m1_t t;} /* { dg-error {unknown type name 'vfloat64m1_t'} } */
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void foo63 () {vfloat64m2_t t;} /* { dg-error {unknown type name 'vfloat64m2_t'} } */
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void foo64 () {vfloat64m4_t t;} /* { dg-error {unknown type name 'vfloat64m4_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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void foo65 () {vfloat64m8_t t;} /* { dg-error {unknown type name 'vfloat64m8_t'} } */
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@ -23,4 +23,4 @@ unsigned long vread_csr_vcsr(void) {
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/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vstart} 1 } } */
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/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vxsat} 1 } } */
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/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vxrm} 1 } } */
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/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vcsr} 1 } } */
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/* { dg-final { scan-assembler-times {csrr\s+(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7]),\s*vcsr} 1 } } */
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@ -23,4 +23,4 @@ void vwrite_csr_vcsr(unsigned long value) {
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/* { dg-final { scan-assembler-times {csrw\s+vstart,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
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/* { dg-final { scan-assembler-times {csrw\s+vxsat,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
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/* { dg-final { scan-assembler-times {csrw\s+vxrm,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
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/* { dg-final { scan-assembler-times {csrw\s+vcsr,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
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/* { dg-final { scan-assembler-times {csrw\s+vcsr,\s*(?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])} 1 } } */
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