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Port testsuite to GCN

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This collection of miscellaneous patches configures the testsuite to run on AMD
GCN in a standalone (i.e. not offloading) configuration.  It assumes you have
your Dejagnu set up to run binaries via the gcn-run tool.

2019-01-17  Andrew Stubbs  <ams@codesourcery.com>
	    Kwok Cheung Yeung  <kcy@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Tom de Vries  <tom@codesourcery.com>

	gcc/
	* doc/sourcebuild.texi: Document dg-add-options sqrt_insn.

	gcc/testsuite/
	* gcc.dg/20020312-2.c: Add amdgcn support.
	* gcc.dg/Wno-frame-address.c: Disable on amdgcn.
	* gcc.dg/builtin-apply2.c: Likewise.
	* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
	* gcc.dg/gimplefe-28.c: Add dg-add-options for sqrt_insn.
	* gcc.dg/intermod-1.c: Add -mlocal-symbol-id on amdgcn.
	* gcc.dg/memcmp-1.c: Increase timeout factor.
	* gcc.dg/pr59605-2.c: Addd -DMAX_COPY=1025 on amdgcn.
	* gcc.dg/sibcall-10.c: xfail on amdgcn.
	* gcc.dg/sibcall-9.c: Likewise.
	* gcc.dg/tree-ssa/gen-vect-11c.c: Likewise.
	* gcc.dg/tree-ssa/pr84512.c: Likewise.
	* gcc.dg/tree-ssa/loop-1.c: Adjust expectations for amdgcn.
	* gfortran.dg/bind_c_array_params_2.f90: Likewise.
	* lib/target-supports.exp (check_effective_target_trampolines):
	Configure amdgcn.
	(check_profiling_available): Likewise.
	(check_effective_target_global_constructor): Likewise.
	(check_effective_target_return_address): Likewise.
	(check_effective_target_fopenacc): Likewise.
	(check_effective_target_fopenmp): Likewise.
	(check_effective_target_vect_int): Likewise.
	(check_effective_target_vect_intfloat_cvt): Likewise.
	(check_effective_target_vect_uintfloat_cvt): Likewise.
	(check_effective_target_vect_floatint_cvt): Likewise.
	(check_effective_target_vect_floatuint_cvt): Likewise.
	(check_effective_target_vect_simd_clones): Likewise.
	(check_effective_target_vect_shift): Likewise.
	(check_effective_target_whole_vector_shift): Likewise.
	(check_effective_target_vect_bswap): Likewise.
	(check_effective_target_vect_shift_char): Likewise.
	(check_effective_target_vect_long): Likewise.
	(check_effective_target_vect_float): Likewise.
	(check_effective_target_vect_double): Likewise.
	(check_effective_target_vect_perm): Likewise.
	(check_effective_target_vect_perm_byte): Likewise.
	(check_effective_target_vect_perm_short): Likewise.
	(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
	(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
	(check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise.
	(check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise.
	(check_effective_target_vect_natural_alignment): Likewise.
	(check_effective_target_vect_fully_masked): Likewise.
	(check_effective_target_vect_element_align): Likewise.
	(check_effective_target_vect_masked_store): Likewise.
	(check_effective_target_vect_scatter_store): Likewise.
	(check_effective_target_vect_condition): Likewise.
	(check_effective_target_vect_cond_mixed): Likewise.
	(check_effective_target_vect_char_mult): Likewise.
	(check_effective_target_vect_short_mult): Likewise.
	(check_effective_target_vect_int_mult): Likewise.
	(check_effective_target_sqrt_insn): Likewise.
	(check_effective_target_vect_call_sqrtf): Likewise.
	(check_effective_target_vect_call_btrunc): Likewise.
	(check_effective_target_vect_call_btruncf): Likewise.
	(check_effective_target_vect_call_ceil): Likewise.
	(check_effective_target_vect_call_floorf): Likewise.
	(check_effective_target_lto): Likewise.
	(check_vect_support_and_set_flags): Likewise.
	(check_effective_target_vect_stridedN): Enable when fully masked is
	available.
	(add_options_for_sqrt_insn): New procedure.


Co-Authored-By: Julian Brown <julian@codesourcery.com>
Co-Authored-By: Kwok Cheung Yeung <kcy@codesourcery.com>
Co-Authored-By: Tom de Vries <tom@codesourcery.com>

From-SVN: r268028
This commit is contained in:
Andrew Stubbs 2019-01-17 12:37:57 +00:00 committed by Andrew Stubbs
parent b50002c4ef
commit 674931d2b7
18 changed files with 199 additions and 48 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2019-01-17 Andrew Stubbs <ams@codesourcery.com>
Kwok Cheung Yeung <kcy@codesourcery.com>
Julian Brown <julian@codesourcery.com>
Tom de Vries <tom@codesourcery.com>
* doc/sourcebuild.texi: Document dg-add-options sqrt_insn.
2019-01-17 Andrew Stubbs <ams@codesourcery.com>
* doc/sourcebuild.texi: Document dg-require-effective-target

4
gcc/doc/sourcebuild.texi
View File

@ -2522,6 +2522,10 @@ Add the flags needed to define macro STACK_SIZE and set it to the stack size
limit associated with the @ref{stack_size_et,,@code{stack_size} effective
target}.
@item sqrt_insn
Add the target-specific flags needed to enable hardware square root
instructions, if any.
@item tls
Add the target-specific flags needed to use thread-local storage.
@end table

68
gcc/testsuite/ChangeLog
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@ -1,3 +1,71 @@
2019-01-17 Andrew Stubbs <ams@codesourcery.com>
Kwok Cheung Yeung <kcy@codesourcery.com>
Julian Brown <julian@codesourcery.com>
Tom de Vries <tom@codesourcery.com>
* gcc.dg/20020312-2.c: Add amdgcn support.
* gcc.dg/Wno-frame-address.c: Disable on amdgcn.
* gcc.dg/builtin-apply2.c: Likewise.
* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
* gcc.dg/gimplefe-28.c: Add dg-add-options for sqrt_insn.
* gcc.dg/intermod-1.c: Add -mlocal-symbol-id on amdgcn.
* gcc.dg/memcmp-1.c: Increase timeout factor.
* gcc.dg/pr59605-2.c: Addd -DMAX_COPY=1025 on amdgcn.
* gcc.dg/sibcall-10.c: xfail on amdgcn.
* gcc.dg/sibcall-9.c: Likewise.
* gcc.dg/tree-ssa/gen-vect-11c.c: Likewise.
* gcc.dg/tree-ssa/pr84512.c: Likewise.
* gcc.dg/tree-ssa/loop-1.c: Adjust expectations for amdgcn.
* gfortran.dg/bind_c_array_params_2.f90: Likewise.
* lib/target-supports.exp (check_effective_target_trampolines):
Configure amdgcn.
(check_profiling_available): Likewise.
(check_effective_target_global_constructor): Likewise.
(check_effective_target_return_address): Likewise.
(check_effective_target_fopenacc): Likewise.
(check_effective_target_fopenmp): Likewise.
(check_effective_target_vect_int): Likewise.
(check_effective_target_vect_intfloat_cvt): Likewise.
(check_effective_target_vect_uintfloat_cvt): Likewise.
(check_effective_target_vect_floatint_cvt): Likewise.
(check_effective_target_vect_floatuint_cvt): Likewise.
(check_effective_target_vect_simd_clones): Likewise.
(check_effective_target_vect_shift): Likewise.
(check_effective_target_whole_vector_shift): Likewise.
(check_effective_target_vect_bswap): Likewise.
(check_effective_target_vect_shift_char): Likewise.
(check_effective_target_vect_long): Likewise.
(check_effective_target_vect_float): Likewise.
(check_effective_target_vect_double): Likewise.
(check_effective_target_vect_perm): Likewise.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
(check_effective_target_vect_widen_mult_qi_to_hi): Likewise.
(check_effective_target_vect_widen_mult_hi_to_si): Likewise.
(check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise.
(check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise.
(check_effective_target_vect_natural_alignment): Likewise.
(check_effective_target_vect_fully_masked): Likewise.
(check_effective_target_vect_element_align): Likewise.
(check_effective_target_vect_masked_store): Likewise.
(check_effective_target_vect_scatter_store): Likewise.
(check_effective_target_vect_condition): Likewise.
(check_effective_target_vect_cond_mixed): Likewise.
(check_effective_target_vect_char_mult): Likewise.
(check_effective_target_vect_short_mult): Likewise.
(check_effective_target_vect_int_mult): Likewise.
(check_effective_target_sqrt_insn): Likewise.
(check_effective_target_vect_call_sqrtf): Likewise.
(check_effective_target_vect_call_btrunc): Likewise.
(check_effective_target_vect_call_btruncf): Likewise.
(check_effective_target_vect_call_ceil): Likewise.
(check_effective_target_vect_call_floorf): Likewise.
(check_effective_target_lto): Likewise.
(check_vect_support_and_set_flags): Likewise.
(check_effective_target_vect_stridedN): Enable when fully masked is
available.
(add_options_for_sqrt_insn): New procedure.
2019-01-17 Andrew Stubbs <ams@codesourcery.com>
* lib/file-format.exp (gcc_target_object_format): Handle AMD GCN.

2
gcc/testsuite/gcc.dg/20020312-2.c
View File

@ -119,6 +119,8 @@ extern void abort (void);
# endif
#elif defined (__or1k__)
/* No pic register. */
#elif defined (__AMDGCN__)
/* No pic register. */
#else
# error "Modify the test for your target."
#endif

2
gcc/testsuite/gcc.dg/Wno-frame-address.c
View File

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-skip-if "Cannot access arbitrary stack frames" { arm*-*-* avr-*-* hppa*-*-* ia64-*-* visium-*-* csky-*-* msp430-*-* } } */
/* { dg-skip-if "Cannot access arbitrary stack frames" { arm*-*-* amdgpu-*-* avr-*-* hppa*-*-* ia64-*-* visium-*-* csky-*-* msp430-*-* } } */
/* { dg-options "-Werror" } */
/* { dg-additional-options "-mbackchain" { target { s390*-*-* } } } */

2
gcc/testsuite/gcc.dg/builtin-apply2.c
View File

@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-require-effective-target untyped_assembly } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-*" } } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-* amdgcn-*-*" } } */
/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-* or1k*-*-* msp430-*-*" } } */
/* { dg-skip-if "Variadic funcs use Base AAPCS. Normal funcs use VFP variant." { arm*-*-* && arm_hf_eabi } } */

1
gcc/testsuite/gcc.dg/gimplefe-28.c
View File

@ -1,5 +1,6 @@
/* { dg-do compile { target sqrt_insn } } */
/* { dg-options "-fgimple -O2" } */
/* { dg-add-options sqrt_insn } */
double __GIMPLE
f1 (double x)

1
gcc/testsuite/gcc.dg/intermod-1.c
View File

@ -1,4 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-mlocal-symbol-id=" { target amdgcn-*-* } } */
/* { dg-final { scan-assembler-not {foo[1-9]\.[0-9]} } } */
/* Check that we don't get .0 suffixes on static variables when not using

1
gcc/testsuite/gcc.dg/memcmp-1.c
View File

@ -2,6 +2,7 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-require-effective-target ptr32plus } */
/* { dg-timeout-factor 2 } */
#include <stdio.h>
#include <stdlib.h>

2
gcc/testsuite/gcc.dg/pr59605-2.c
View File

@ -1,6 +1,6 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-additional-options "-DMAX_COPY=1025" { target { { simulator } || { nvptx-*-* } } } } */
/* { dg-additional-options "-DMAX_COPY=1025" { target { { simulator } || { nvptx-*-* amdgcn*-*-* } } } } */
/* { dg-additional-options "-minline-stringops-dynamically" { target { i?86-*-* x86_64-*-* } } } */
#include "pr59605.c"

2
gcc/testsuite/gcc.dg/sibcall-10.c
View File

@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
/* { dg-do run { xfail { { cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
/* -msave-restore disables sibcall patterns. */

2
gcc/testsuite/gcc.dg/sibcall-9.c
View File

@ -5,7 +5,7 @@
Copyright (C) 2002 Free Software Foundation Inc.
Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
/* { dg-do run { xfail { { cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* { dg-do run { xfail { { amdgcn*-*-* cris-*-* crisv32-*-* csky-*-* h8300-*-* hppa*64*-*-* m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
/* -msave-restore disables sibcall patterns. */

2
gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
View File

@ -9,7 +9,7 @@
/* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant.
avr: Variadic funcs don't pass arguments in registers, while normal funcs
do. */
/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* or1k*-*-* msp430-*-* } } } */
/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* } } } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } { v850*-*-* } } */
/* { dg-require-effective-target untyped_assembly } */

2
gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
View File

@ -39,4 +39,4 @@ int main ()
}
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail amdgcn*-*-* } } } */

6
gcc/testsuite/gcc.dg/tree-ssa/loop-1.c
View File

@ -45,8 +45,10 @@ int xxx(void)
relaxation. */
/* CRIS and MSP430 keep the address in a register. */
/* m68k sometimes puts the address in a register, depending on CPU and PIC. */
/* AMD GCN loads symbol addresses as hi/lo pairs, and then reuses that for
each jump. */
/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* pdp11*-*-* msp430-*-* } } } */
/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* i?86-*-mingw* i?86-*-cygwin* x86_64-*-mingw* visium-*-* nvptx*-*-* pdp11*-*-* msp430-*-* amdgcn*-*-* } } } */
/* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
/* { dg-final { scan-assembler-times "= foo" 5 { target ia64*-*-* } } } */
/* { dg-final { scan-assembler-times "call\[ \t\]*_foo" 5 { target i?86-*-mingw* i?86-*-cygwin* } } } */
@ -56,3 +58,5 @@ int xxx(void)
/* { dg-final { scan-assembler-times "\[jb\]sr" 5 { target fido-*-* m68k-*-* pdp11-*-* } } } */
/* { dg-final { scan-assembler-times "bra *tr,r\[1-9\]*,r21" 5 { target visium-*-* } } } */
/* { dg-final { scan-assembler-times "(?n)\[ \t\]call\[ \t\].*\[ \t\]foo," 5 { target nvptx*-*-* } } } */
/* { dg-final { scan-assembler-times "add_u32\t\[sv\]\[0-9\]*, \[sv\]\[0-9\]*, foo@rel32@lo" 1 { target { amdgcn*-*-* } } } } */
/* { dg-final { scan-assembler-times "s_swappc_b64" 5 { target { amdgcn*-*-* } } } } */

2
gcc/testsuite/gcc.dg/tree-ssa/pr84512.c
View File

@ -13,4 +13,4 @@ int foo()
}
/* Listed targets xfailed due to PR84958. */
/* { dg-final { scan-tree-dump "return 285;" "optimized" { xfail { { alpha*-*-* nvptx*-*-* } || { sparc*-*-* && lp64 } } } } } */
/* { dg-final { scan-tree-dump "return 285;" "optimized" { xfail { { alpha*-*-* amdgcn*-*-* nvptx*-*-* } || { sparc*-*-* && lp64 } } } } } */

3
gcc/testsuite/gfortran.dg/bind_c_array_params_2.f90
View File

@ -16,8 +16,9 @@ integer :: aa(4,4)
call test(aa)
end
! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* } } } } }
! { dg-final { scan-assembler-times "\[ \t\]\[$,_0-9\]*myBindC" 1 { target { ! { hppa*-*-* s390*-*-* *-*-cygwin* amdgcn*-*-* } } } } }
! { dg-final { scan-assembler-times "myBindC,%r2" 1 { target { hppa*-*-* } } } }
! { dg-final { scan-assembler-times "call\tmyBindC" 1 { target { *-*-cygwin* } } } }
! { dg-final { scan-assembler-times "brasl\t%r\[0-9\]*,myBindC" 1 { target { s390*-*-* } } } }
! { dg-final { scan-assembler-times "add_u32\t\[sv\]\[0-9\]*, \[sv\]\[0-9\]*, myBindC@rel32@lo" 1 { target { amdgcn*-*-* } } } }
! { dg-final { scan-tree-dump-times "cfi_desc_to_gfc_desc \\\(&parm\\." 1 "original" } }

138
gcc/testsuite/lib/target-supports.exp
View File

@ -659,6 +659,7 @@ proc check_profiling_available { test_what } {
# missing other needed machinery.
if {[istarget aarch64*-*-elf]
|| [istarget am3*-*-linux*]
|| [istarget amdgcn-*-*]
|| [istarget arm*-*-eabi*]
|| [istarget arm*-*-elf]
|| [istarget arm*-*-symbianelf*]
@ -784,6 +785,9 @@ proc check_effective_target_global_constructor {} {
if { [istarget nvptx-*-*] } {
return 0
}
if { [istarget amdgcn-*-*] } {
return 0
}
return 1
}
@ -804,6 +808,10 @@ proc check_effective_target_return_address {} {
if { [istarget nvptx-*-*] } {
return 0
}
# It could be supported on amdgcn, but isn't yet.
if { [istarget amdgcn*-*-*] } {
return 0
}
return 1
}
@ -945,9 +953,10 @@ proc check_effective_target_fgraphite {} {
# code, 0 otherwise.
proc check_effective_target_fopenacc {} {
# nvptx can be built with the device-side bits of openacc, but it
# nvptx/amdgcn can be built with the device-side bits of openacc, but it
# does not make sense to test it as an openacc host.
if [istarget nvptx-*-*] { return 0 }
if [istarget amdgcn-*-*] { return 0 }
return [check_no_compiler_messages fopenacc object {
void foo (void) { }
@ -958,9 +967,10 @@ proc check_effective_target_fopenacc {} {
# code, 0 otherwise.
proc check_effective_target_fopenmp {} {
# nvptx can be built with the device-side bits of libgomp, but it
# nvptx/amdgcn can be built with the device-side bits of libgomp, but it
# does not make sense to test it as an openmp host.
if [istarget nvptx-*-*] { return 0 }
if [istarget amdgcn-*-*] { return 0 }
return [check_no_compiler_messages fopenmp object {
void foo (void) { }
@ -3122,6 +3132,7 @@ proc check_effective_target_vect_int { } {
[istarget i?86-*-*] || [istarget x86_64-*-*]
|| ([istarget powerpc*-*-*]
&& ![istarget powerpc-*-linux*paired*])
|| [istarget amdgcn-*-*]
|| [istarget spu-*-*]
|| [istarget sparc*-*-*]
|| [istarget alpha*-*-*]
@ -3146,7 +3157,8 @@ proc check_effective_target_vect_intfloat_cvt { } {
&& ![istarget powerpc-*-linux*paired*])
|| [is-effective-target arm_neon]
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa]) }}]
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports signed double->int conversion
@ -3210,7 +3222,8 @@ proc check_effective_target_vect_uintfloat_cvt { } {
|| [istarget aarch64*-*-*]
|| [is-effective-target arm_neon]
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa]) }}]
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*] }}]
}
@ -3224,7 +3237,8 @@ proc check_effective_target_vect_floatint_cvt { } {
&& ![istarget powerpc-*-linux*paired*])
|| [is-effective-target arm_neon]
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa]) }}]
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports unsigned float->int conversion
@ -3236,7 +3250,8 @@ proc check_effective_target_vect_floatuint_cvt { } {
&& ![istarget powerpc-*-linux*paired*])
|| [is-effective-target arm_neon]
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa]) }}]
&& [et-is-effective-target mips_msa])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if peeling for alignment might be profitable on the target
@ -3260,7 +3275,8 @@ proc check_effective_target_vect_simd_clones { } {
# be able to assemble avx512f.
return [check_cached_effective_target_indexed vect_simd_clones {
expr { (([istarget i?86-*-*] || [istarget x86_64-*-*])
&& [check_effective_target_avx512f]) }}]
&& [check_effective_target_avx512f])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if this is a AArch64 target supporting big endian
@ -5392,7 +5408,8 @@ proc check_effective_target_vect_shift { } {
&& ([et-is-effective-target mips_msa]
|| [et-is-effective-target mips_loongson_mmi]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports hardware vector shift by register operation.
@ -5414,7 +5431,8 @@ proc check_effective_target_whole_vector_shift { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_loongson_mmi])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] } {
set answer 1
} else {
set answer 0
@ -5428,7 +5446,9 @@ proc check_effective_target_whole_vector_shift { } {
proc check_effective_target_vect_bswap { } {
return [check_cached_effective_target_indexed vect_bswap {
expr { [istarget aarch64*-*-*] || [is-effective-target arm_neon] }}]
expr { [istarget aarch64*-*-*]
|| [is-effective-target arm_neon]
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports hardware vector shift operation for char.
@ -5441,7 +5461,8 @@ proc check_effective_target_vect_shift_char { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
@ -5459,7 +5480,8 @@ proc check_effective_target_vect_long { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) } {
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] } {
set answer 1
} else {
set answer 0
@ -5487,7 +5509,8 @@ proc check_effective_target_vect_float { } {
&& [et-is-effective-target mips_msa])
|| [is-effective-target arm_neon]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vxe]) }}]
&& [check_effective_target_s390_vxe])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports hardware vectors of float without
@ -5516,7 +5539,8 @@ proc check_effective_target_vect_double { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])} }]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*]} }]
}
# Return 1 if the target supports conditional addition, subtraction,
@ -5591,7 +5615,8 @@ proc check_effective_target_vect_perm { } {
&& ([et-is-effective-target mpaired_single]
|| [et-is-effective-target mips_msa]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if, for some VF:
@ -5684,7 +5709,8 @@ proc check_effective_target_vect_perm_byte { } {
|| ([istarget mips-*.*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports SLP permutation of 3 vectors when each
@ -5713,7 +5739,8 @@ proc check_effective_target_vect_perm_short { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports SLP permutation of 3 vectors when each
@ -5805,7 +5832,8 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } {
&& ![check_effective_target_aarch64_sve])
|| [is-effective-target arm_neon]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])) }}]
&& [check_effective_target_s390_vx]))
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target plus current options supports a vector
@ -5829,7 +5857,8 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } {
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [is-effective-target arm_neon]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx])) }}]
&& [check_effective_target_s390_vx]))
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target plus current options supports a vector
@ -5843,7 +5872,8 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } {
|| ([is-effective-target arm_neon]
&& [check_effective_target_arm_little_endian])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target plus current options supports a vector
@ -5860,7 +5890,8 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } {
|| ([is-effective-target arm_neon]
&& [check_effective_target_arm_little_endian])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target plus current options supports a vector
@ -6104,7 +6135,8 @@ proc check_effective_target_vect_natural_alignment { } {
set et_vect_natural_alignment 1
if { [check_effective_target_arm_eabi]
|| [istarget nvptx-*-*]
|| [istarget s390*-*-*] } {
|| [istarget s390*-*-*]
|| [istarget amdgcn-*-*] } {
set et_vect_natural_alignment 0
}
verbose "check_effective_target_vect_natural_alignment:\
@ -6115,7 +6147,8 @@ proc check_effective_target_vect_natural_alignment { } {
# Return true if fully-masked loops are supported.
proc check_effective_target_vect_fully_masked { } {
return [check_effective_target_aarch64_sve]
return [expr { [check_effective_target_aarch64_sve]
|| [istarget amdgcn*-*-*] }]
}
# Return 1 if the target doesn't prefer any alignment beyond element
@ -6167,7 +6200,8 @@ proc check_effective_target_vect_element_align { } {
return [check_cached_effective_target_indexed vect_element_align {
expr { ([istarget arm*-*-*]
&& ![check_effective_target_arm_vect_no_misalign])
|| [check_effective_target_vect_hw_misalign] }}]
|| [check_effective_target_vect_hw_misalign]
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if we expect to see unaligned accesses in at least some
@ -6192,13 +6226,15 @@ proc check_effective_target_vect_load_lanes { } {
# Return 1 if the target supports vector masked stores.
proc check_effective_target_vect_masked_store { } {
return [check_effective_target_aarch64_sve]
return [expr { [check_effective_target_aarch64_sve]
|| [istarget amdgcn*-*-*] }]
}
# Return 1 if the target supports vector scatter stores.
proc check_effective_target_vect_scatter_store { } {
return [check_effective_target_aarch64_sve]
return [expr { [check_effective_target_aarch64_sve]
|| [istarget amdgcn*-*-*] }]
}
# Return 1 if the target supports vector conditional operations, 0 otherwise.
@ -6215,7 +6251,8 @@ proc check_effective_target_vect_condition { } {
|| ([istarget arm*-*-*]
&& [check_effective_target_arm_neon_ok])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector conditional operations where
@ -6229,7 +6266,8 @@ proc check_effective_target_vect_cond_mixed { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector char multiplication, 0 otherwise.
@ -6244,7 +6282,8 @@ proc check_effective_target_vect_char_mult { } {
|| ([istarget mips*-*-*]
&& [et-is-effective-target mips_msa])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector short multiplication, 0 otherwise.
@ -6261,7 +6300,8 @@ proc check_effective_target_vect_short_mult { } {
&& ([et-is-effective-target mips_msa]
|| [et-is-effective-target mips_loongson_mmi]))
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector int multiplication, 0 otherwise.
@ -6277,7 +6317,8 @@ proc check_effective_target_vect_int_mult { } {
&& [et-is-effective-target mips_msa])
|| [check_effective_target_arm32]
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports 64 bit hardware vector
@ -6352,6 +6393,9 @@ foreach N {2 3 4 8} {
|| [istarget aarch64*-*-*]) && N >= 2 && N <= 4 } {
return 1
}
if [check_effective_target_vect_fully_masked] {
return 1
}
return 0
}]
}
@ -6419,7 +6463,17 @@ proc check_effective_target_sqrt_insn { } {
|| [istarget aarch64*-*-*]
|| ([istarget arm*-*-*] && [check_effective_target_arm_vfp_ok])
|| ([istarget s390*-*-*]
&& [check_effective_target_s390_vx]) }}]
&& [check_effective_target_s390_vx])
|| [istarget amdgcn-*-*] }}]
}
# Return any additional options to enable square root intructions.
proc add_options_for_sqrt_insn { flags } {
if { [istarget amdgcn*-*-*] } {
return "$flags -ffast-math"
}
return $flags
}
# Return 1 if the target supports vector sqrtf calls.
@ -6438,7 +6492,8 @@ proc check_effective_target_vect_call_sqrtf { } {
proc check_effective_target_vect_call_lrint { } {
set et_vect_call_lrint 0
if { (([istarget i?86-*-*] || [istarget x86_64-*-*])
&& [check_effective_target_ilp32]) } {
&& [check_effective_target_ilp32])
|| [istarget amdgcn-*-*] } {
set et_vect_call_lrint 1
}
@ -6450,21 +6505,24 @@ proc check_effective_target_vect_call_lrint { } {
proc check_effective_target_vect_call_btrunc { } {
return [check_cached_effective_target_indexed vect_call_btrunc {
expr { [istarget aarch64*-*-*] }}]
expr { [istarget aarch64*-*-*]
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector btruncf calls.
proc check_effective_target_vect_call_btruncf { } {
return [check_cached_effective_target_indexed vect_call_btruncf {
expr { [istarget aarch64*-*-*] }}]
expr { [istarget aarch64*-*-*]
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector ceil calls.
proc check_effective_target_vect_call_ceil { } {
return [check_cached_effective_target_indexed vect_call_ceil {
expr { [istarget aarch64*-*-*] }}]
expr { [istarget aarch64*-*-*]
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector ceilf calls.
@ -6485,7 +6543,8 @@ proc check_effective_target_vect_call_floor { } {
proc check_effective_target_vect_call_floorf { } {
return [check_cached_effective_target_indexed vect_call_floorf {
expr { [istarget aarch64*-*-*] }}]
expr { [istarget aarch64*-*-*]
|| [istarget amdgcn-*-*] }}]
}
# Return 1 if the target supports vector lceil calls.
@ -8032,7 +8091,8 @@ proc check_effective_target_gld { } {
# (LTO) support.
proc check_effective_target_lto { } {
if { [istarget nvptx-*-*] } {
if { [istarget nvptx-*-*]
|| [istarget amdgcn-*-*] } {
return 0;
}
return [check_no_compiler_messages lto object {
@ -8362,6 +8422,8 @@ proc check_vect_support_and_set_flags { } {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
set dg-do-what-default compile
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
} else {
return 0
}