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Add execution + assembler tests of AArch64 UZP Intrinsics.

Browse Source 
* gcc.target/aarch64/simd/vuzpf32_1.c: New file.
	* gcc.target/aarch64/simd/vuzpf32.x: New file.
	* gcc.target/aarch64/simd/vuzpp16_1.c: New file.
	* gcc.target/aarch64/simd/vuzpp16.x: New file.
	* gcc.target/aarch64/simd/vuzpp8_1.c: New file.
	* gcc.target/aarch64/simd/vuzpp8.x: New file.
	* gcc.target/aarch64/simd/vuzpqf32_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqf32.x: New file.
	* gcc.target/aarch64/simd/vuzpqp16_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqp16.x: New file.
	* gcc.target/aarch64/simd/vuzpqp8_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqp8.x: New file.
	* gcc.target/aarch64/simd/vuzpqs16_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqs16.x: New file.
	* gcc.target/aarch64/simd/vuzpqs32_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqs32.x: New file.
	* gcc.target/aarch64/simd/vuzpqs8_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqs8.x: New file.
	* gcc.target/aarch64/simd/vuzpqu16_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqu16.x: New file.
	* gcc.target/aarch64/simd/vuzpqu32_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqu32.x: New file.
	* gcc.target/aarch64/simd/vuzpqu8_1.c: New file.
	* gcc.target/aarch64/simd/vuzpqu8.x: New file.
	* gcc.target/aarch64/simd/vuzps16_1.c: New file.
	* gcc.target/aarch64/simd/vuzps16.x: New file.
	* gcc.target/aarch64/simd/vuzps32_1.c: New file.
	* gcc.target/aarch64/simd/vuzps32.x: New file.
	* gcc.target/aarch64/simd/vuzps8_1.c: New file.
	* gcc.target/aarch64/simd/vuzps8.x: New file.
	* gcc.target/aarch64/simd/vuzpu16_1.c: New file.
	* gcc.target/aarch64/simd/vuzpu16.x: New file.
	* gcc.target/aarch64/simd/vuzpu32_1.c: New file.
	* gcc.target/aarch64/simd/vuzpu32.x: New file.
	* gcc.target/aarch64/simd/vuzpu8_1.c: New file.
	* gcc.target/aarch64/simd/vuzpu8.x: New file.

From-SVN: r209940
This commit is contained in:
Alan Lawrence 2014-04-30 16:36:07 +00:00 committed by Alan Lawrence
parent e5bd20a4f1
commit 6657487103
37 changed files with 708 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
gcc/testsuite/ChangeLog
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@ -1,3 +1,42 @@
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/vuzpf32_1.c: New file.
* gcc.target/aarch64/simd/vuzpf32.x: New file.
* gcc.target/aarch64/simd/vuzpp16_1.c: New file.
* gcc.target/aarch64/simd/vuzpp16.x: New file.
* gcc.target/aarch64/simd/vuzpp8_1.c: New file.
* gcc.target/aarch64/simd/vuzpp8.x: New file.
* gcc.target/aarch64/simd/vuzpqf32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqf32.x: New file.
* gcc.target/aarch64/simd/vuzpqp16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqp16.x: New file.
* gcc.target/aarch64/simd/vuzpqp8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqp8.x: New file.
* gcc.target/aarch64/simd/vuzpqs16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs16.x: New file.
* gcc.target/aarch64/simd/vuzpqs32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs32.x: New file.
* gcc.target/aarch64/simd/vuzpqs8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs8.x: New file.
* gcc.target/aarch64/simd/vuzpqu16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu16.x: New file.
* gcc.target/aarch64/simd/vuzpqu32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu32.x: New file.
* gcc.target/aarch64/simd/vuzpqu8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu8.x: New file.
* gcc.target/aarch64/simd/vuzps16_1.c: New file.
* gcc.target/aarch64/simd/vuzps16.x: New file.
* gcc.target/aarch64/simd/vuzps32_1.c: New file.
* gcc.target/aarch64/simd/vuzps32.x: New file.
* gcc.target/aarch64/simd/vuzps8_1.c: New file.
* gcc.target/aarch64/simd/vuzps8.x: New file.
* gcc.target/aarch64/simd/vuzpu16_1.c: New file.
* gcc.target/aarch64/simd/vuzpu16.x: New file.
* gcc.target/aarch64/simd/vuzpu32_1.c: New file.
* gcc.target/aarch64/simd/vuzpu32.x: New file.
* gcc.target/aarch64/simd/vuzpu8_1.c: New file.
* gcc.target/aarch64/simd/vuzpu8.x: New file.
2014-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/48329

26
gcc/testsuite/gcc.target/aarch64/simd/vuzpf32.x Normal file
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extern void abort (void);
float32x2x2_t
test_vuzpf32 (float32x2_t _a, float32x2_t _b)
{
return vuzp_f32 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
float32_t first[] = {1, 2};
float32_t second[] = {3, 4};
float32x2x2_t result = test_vuzpf32 (vld1_f32 (first), vld1_f32 (second));
float32_t exp1[] = {1, 3};
float32_t exp2[] = {2, 4};
float32x2_t expect1 = vld1_f32 (exp1);
float32x2_t expect2 = vld1_f32 (exp2);
for (i = 0; i < 2; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpf32_1.c Normal file
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/* Test the `vuzp_f32' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpf32.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

26
gcc/testsuite/gcc.target/aarch64/simd/vuzpp16.x Normal file
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extern void abort (void);
poly16x4x2_t
test_vuzpp16 (poly16x4_t _a, poly16x4_t _b)
{
return vuzp_p16 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
poly16_t first[] = {1, 2, 3, 4};
poly16_t second[] = {5, 6, 7, 8};
poly16x4x2_t result = test_vuzpp16 (vld1_p16 (first), vld1_p16 (second));
poly16_t exp1[] = {1, 3, 5, 7};
poly16_t exp2[] = {2, 4, 6, 8};
poly16x4_t expect1 = vld1_p16 (exp1);
poly16x4_t expect2 = vld1_p16 (exp2);
for (i = 0; i < 4; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpp16_1.c Normal file
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@ -0,0 +1,11 @@
/* Test the `vuzp_p16' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpp16.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

26
gcc/testsuite/gcc.target/aarch64/simd/vuzpp8.x Normal file
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extern void abort (void);
poly8x8x2_t
test_vuzpp8 (poly8x8_t _a, poly8x8_t _b)
{
return vuzp_p8 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
poly8x8x2_t result = test_vuzpp8 (vld1_p8 (first), vld1_p8 (second));
poly8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
poly8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
poly8x8_t expect1 = vld1_p8 (exp1);
poly8x8_t expect2 = vld1_p8 (exp2);
for (i = 0; i < 8; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpp8_1.c Normal file
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/* Test the `vuzp_p8' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpp8.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

26
gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32.x Normal file
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extern void abort (void);
float32x4x2_t
test_vuzpqf32 (float32x4_t _a, float32x4_t _b)
{
return vuzpq_f32 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
float32_t first[] = {1, 2, 3, 4};
float32_t second[] = {5, 6, 7, 8};
float32x4x2_t result = test_vuzpqf32 (vld1q_f32 (first), vld1q_f32 (second));
float32_t exp1[] = {1, 3, 5, 7};
float32_t exp2[] = {2, 4, 6, 8};
float32x4_t expect1 = vld1q_f32 (exp1);
float32x4_t expect2 = vld1q_f32 (exp2);
for (i = 0; i < 4; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32_1.c Normal file
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/* Test the `vuzpq_f32' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqf32.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16.x Normal file
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extern void abort (void);
poly16x8x2_t
test_vuzpqp16 (poly16x8_t _a, poly16x8_t _b)
{
return vuzpq_p16 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
poly16x8x2_t result = test_vuzpqp16 (vld1q_p16 (first), vld1q_p16 (second));
poly16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
poly16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
poly16x8_t expect1 = vld1q_p16 (exp1);
poly16x8_t expect2 = vld1q_p16 (exp2);
for (i = 0; i < 8; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16_1.c Normal file
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/* Test the `vuzpq_p16' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqp16.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8.x Normal file
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extern void abort (void);
poly8x16x2_t
test_vuzpqp8 (poly8x16_t _a, poly8x16_t _b)
{
return vuzpq_p8 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
poly8_t second[] =
{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
poly8x16x2_t result = test_vuzpqp8 (vld1q_p8 (first), vld1q_p8 (second));
poly8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31};
poly8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
poly8x16_t expect1 = vld1q_p8 (exp1);
poly8x16_t expect2 = vld1q_p8 (exp2);
for (i = 0; i < 16; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8_1.c Normal file
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/* Test the `vuzpq_p8' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqp8.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16.x Normal file
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extern void abort (void);
int16x8x2_t
test_vuzpqs16 (int16x8_t _a, int16x8_t _b)
{
return vuzpq_s16 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
int16x8x2_t result = test_vuzpqs16 (vld1q_s16 (first), vld1q_s16 (second));
int16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
int16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
int16x8_t expect1 = vld1q_s16 (exp1);
int16x8_t expect2 = vld1q_s16 (exp2);
for (i = 0; i < 8; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16_1.c Normal file
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/* Test the `vuzpq_s16' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqs16.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32.x Normal file
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extern void abort (void);
int32x4x2_t
test_vuzpqs32 (int32x4_t _a, int32x4_t _b)
{
return vuzpq_s32 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
int32_t first[] = {1, 2, 3, 4};
int32_t second[] = {5, 6, 7, 8};
int32x4x2_t result = test_vuzpqs32 (vld1q_s32 (first), vld1q_s32 (second));
int32_t exp1[] = {1, 3, 5, 7};
int32_t exp2[] = {2, 4, 6, 8};
int32x4_t expect1 = vld1q_s32 (exp1);
int32x4_t expect2 = vld1q_s32 (exp2);
for (i = 0; i < 4; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32_1.c Normal file
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/* Test the `vuzpq_s32' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqs32.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8.x Normal file
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extern void abort (void);
int8x16x2_t
test_vuzpqs8 (int8x16_t _a, int8x16_t _b)
{
return vuzpq_s8 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
int8_t second[] =
{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
int8x16x2_t result = test_vuzpqs8 (vld1q_s8 (first), vld1q_s8 (second));
int8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31};
int8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
int8x16_t expect1 = vld1q_s8 (exp1);
int8x16_t expect2 = vld1q_s8 (exp2);
for (i = 0; i < 16; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8_1.c Normal file
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/* Test the `vuzpq_s8' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqs8.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
uint16x8x2_t
test_vuzpqu16 (uint16x8_t _a, uint16x8_t _b)
{
return vuzpq_u16 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
uint16x8x2_t result = test_vuzpqu16 (vld1q_u16 (first), vld1q_u16 (second));
uint16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
uint16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
uint16x8_t expect1 = vld1q_u16 (exp1);
uint16x8_t expect2 = vld1q_u16 (exp2);
for (i = 0; i < 8; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
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/* Test the `vuzpq_u16' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqu16.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
uint32x4x2_t
test_vuzpqu32 (uint32x4_t _a, uint32x4_t _b)
{
return vuzpq_u32 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
uint32_t first[] = {1, 2, 3, 4};
uint32_t second[] = {5, 6, 7, 8};
uint32x4x2_t result = test_vuzpqu32 (vld1q_u32 (first), vld1q_u32 (second));
uint32_t exp1[] = {1, 3, 5, 7};
uint32_t exp2[] = {2, 4, 6, 8};
uint32x4_t expect1 = vld1q_u32 (exp1);
uint32x4_t expect2 = vld1q_u32 (exp2);
for (i = 0; i < 4; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32_1.c Normal file
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/* Test the `vuzpq_u32' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqu32.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
uint8x16x2_t
test_vuzpqu8 (uint8x16_t _a, uint8x16_t _b)
{
return vuzpq_u8 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
uint8_t second[] =
{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
uint8x16x2_t result = test_vuzpqu8 (vld1q_u8 (first), vld1q_u8 (second));
uint8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31};
uint8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
uint8x16_t expect1 = vld1q_u8 (exp1);
uint8x16_t expect2 = vld1q_u8 (exp2);
for (i = 0; i < 16; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

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gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8_1.c Normal file
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/* Test the `vuzpq_u8' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpqu8.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
int16x4x2_t
test_vuzps16 (int16x4_t _a, int16x4_t _b)
{
return vuzp_s16 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
int16_t first[] = {1, 2, 3, 4};
int16_t second[] = {5, 6, 7, 8};
int16x4x2_t result = test_vuzps16 (vld1_s16 (first), vld1_s16 (second));
int16_t exp1[] = {1, 3, 5, 7};
int16_t exp2[] = {2, 4, 6, 8};
int16x4_t expect1 = vld1_s16 (exp1);
int16x4_t expect2 = vld1_s16 (exp2);
for (i = 0; i < 4; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzps16_1.c Normal file
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/* Test the `vuzp_s16' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzps16.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
int32x2x2_t
test_vuzps32 (int32x2_t _a, int32x2_t _b)
{
return vuzp_s32 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
int32_t first[] = {1, 2};
int32_t second[] = {3, 4};
int32x2x2_t result = test_vuzps32 (vld1_s32 (first), vld1_s32 (second));
int32_t exp1[] = {1, 3};
int32_t exp2[] = {2, 4};
int32x2_t expect1 = vld1_s32 (exp1);
int32x2_t expect2 = vld1_s32 (exp2);
for (i = 0; i < 2; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzps32_1.c Normal file
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/* Test the `vuzp_s32' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzps32.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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gcc/testsuite/gcc.target/aarch64/simd/vuzps8.x Normal file
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extern void abort (void);
int8x8x2_t
test_vuzps8 (int8x8_t _a, int8x8_t _b)
{
return vuzp_s8 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
int8x8x2_t result = test_vuzps8 (vld1_s8 (first), vld1_s8 (second));
int8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
int8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
int8x8_t expect1 = vld1_s8 (exp1);
int8x8_t expect2 = vld1_s8 (exp2);
for (i = 0; i < 8; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzps8_1.c Normal file
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/* Test the `vuzp_s8' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzps8.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
uint16x4x2_t
test_vuzpu16 (uint16x4_t _a, uint16x4_t _b)
{
return vuzp_u16 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
uint16_t first[] = {1, 2, 3, 4};
uint16_t second[] = {5, 6, 7, 8};
uint16x4x2_t result = test_vuzpu16 (vld1_u16 (first), vld1_u16 (second));
uint16_t exp1[] = {1, 3, 5, 7};
uint16_t exp2[] = {2, 4, 6, 8};
uint16x4_t expect1 = vld1_u16 (exp1);
uint16x4_t expect2 = vld1_u16 (exp2);
for (i = 0; i < 4; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpu16_1.c Normal file
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/* Test the `vuzp_u16' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpu16.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
uint32x2x2_t
test_vuzpu32 (uint32x2_t _a, uint32x2_t _b)
{
return vuzp_u32 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
uint32_t first[] = {1, 2};
uint32_t second[] = {3, 4};
uint32x2x2_t result = test_vuzpu32 (vld1_u32 (first), vld1_u32 (second));
uint32_t exp1[] = {1, 3};
uint32_t exp2[] = {2, 4};
uint32x2_t expect1 = vld1_u32 (exp1);
uint32x2_t expect2 = vld1_u32 (exp2);
for (i = 0; i < 2; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

11
gcc/testsuite/gcc.target/aarch64/simd/vuzpu32_1.c Normal file
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/* Test the `vuzp_u32' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpu32.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */

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extern void abort (void);
uint8x8x2_t
test_vuzpu8 (uint8x8_t _a, uint8x8_t _b)
{
return vuzp_u8 (_a, _b);
}
int
main (int argc, char **argv)
{
int i;
uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
uint8x8x2_t result = test_vuzpu8 (vld1_u8 (first), vld1_u8 (second));
uint8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15};
uint8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16};
uint8x8_t expect1 = vld1_u8 (exp1);
uint8x8_t expect2 = vld1_u8 (exp2);
for (i = 0; i < 8; i++)
if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i]))
abort ();
return 0;
}

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gcc/testsuite/gcc.target/aarch64/simd/vuzpu8_1.c Normal file
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/* Test the `vuzp_u8' AArch64 SIMD intrinsic. */
/* { dg-do run } */
/* { dg-options "-save-temps -fno-inline" } */
#include <arm_neon.h>
#include "vuzpu8.x"
/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
/* { dg-final { cleanup-saved-temps } } */