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rs6000-protos.h: Rename output_e500_flip_eq_bit to output_e500_flip_gt_bit.
* config/rs6000/rs6000-protos.h: Rename output_e500_flip_eq_bit to
output_e500_flip_gt_bit.
* config/rs6000/rs6000.c (print_operand): case D: Print out bit 31
as bit 31.
(rs6000_generate_compare): Fix logic to look at the correct bits.
(output_e500_flip_eq_bit): Rename to output_e500_flip_gt_bit.
Look at GT bit.
(rs6000_emit_sCOND): Rename gen_e500_flip_eq_bit to
gen_e500_flip_gt_bit. Rename gen_move_from_CR_eq_bit to
gen_move_from_CR_gt_bit.
* config/rs6000/rs6000.md ("move_from_CR_eq_bit"): Change bit
("move_from_CR_eq_bit"): Rename to move_from_CR_gt_bit.
(UNSPEC_MV_CR_EQ): Rename to UNSPEC_MV_CR_GT.
* config/rs6000/spe.md ("e500_cr_ior_compare"): New.
(E500_CR_IOR_COMPARE): New constant.
[[Split portion of a mixed commit.]]
From-SVN: r96063.2
This commit is contained in:
Aldy Hernandez
Aldy Hernandez
parent
2125de9340
commit
64022b5db4
@ -1,3 +1,24 @@
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2005-03-07 Aldy Hernandez <aldyh@redhat.com>
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* config/rs6000/rs6000-protos.h: Rename output_e500_flip_eq_bit to
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output_e500_flip_gt_bit.
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* config/rs6000/rs6000.c (print_operand): case D: Print out bit 31
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as bit 31.
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(rs6000_generate_compare): Fix logic to look at the correct bits.
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(output_e500_flip_eq_bit): Rename to output_e500_flip_gt_bit.
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Look at GT bit.
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(rs6000_emit_sCOND): Rename gen_e500_flip_eq_bit to
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gen_e500_flip_gt_bit. Rename gen_move_from_CR_eq_bit to
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gen_move_from_CR_gt_bit.
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* config/rs6000/rs6000.md ("move_from_CR_eq_bit"): Change bit
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("move_from_CR_eq_bit"): Rename to move_from_CR_gt_bit.
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(UNSPEC_MV_CR_EQ): Rename to UNSPEC_MV_CR_GT.
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* config/rs6000/spe.md ("e500_cr_ior_compare"): New.
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(E500_CR_IOR_COMPARE): New constant.
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2005-03-08 Earl Chew <earl_chew@agilent.com>
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David Billinghurst <David.Billinghurst@riotinto.com>
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@ -76,7 +76,7 @@ extern enum rtx_code rs6000_reverse_condition (enum machine_mode,
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extern void rs6000_emit_sCOND (enum rtx_code, rtx);
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extern void rs6000_emit_cbranch (enum rtx_code, rtx);
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extern char * output_cbranch (rtx, const char *, int, rtx);
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extern char * output_e500_flip_eq_bit (rtx, rtx);
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extern char * output_e500_flip_gt_bit (rtx, rtx);
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extern rtx rs6000_emit_set_const (rtx, enum machine_mode, rtx, int);
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extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
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extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx);
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@ -9211,8 +9211,7 @@ print_operand (FILE *file, rtx x, int code)
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/* Bit 1 is EQ bit. */
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i = 4 * (REGNO (x) - CR0_REGNO) + 2;
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/* If we want bit 31, write a shift count of zero, not 32. */
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fprintf (file, "%d", i == 31 ? 0 : i + 1);
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fprintf (file, "%d", i);
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return;
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case 'E':
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@ -10017,7 +10016,7 @@ rs6000_generate_compare (enum rtx_code code)
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if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
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&& rs6000_compare_fp_p)
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{
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rtx cmp, or1, or2, or_result, compare_result2;
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rtx cmp, or_result, compare_result2;
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enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
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if (op_mode == VOIDmode)
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@ -10091,9 +10090,6 @@ rs6000_generate_compare (enum rtx_code code)
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default: abort ();
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}
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or1 = gen_reg_rtx (SImode);
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or2 = gen_reg_rtx (SImode);
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or_result = gen_reg_rtx (CCEQmode);
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compare_result2 = gen_reg_rtx (CCFPmode);
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/* Do the EQ. */
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@ -10112,14 +10108,10 @@ rs6000_generate_compare (enum rtx_code code)
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else abort ();
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emit_insn (cmp);
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or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
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or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
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/* OR them together. */
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cmp = gen_rtx_SET (VOIDmode, or_result,
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gen_rtx_COMPARE (CCEQmode,
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gen_rtx_IOR (SImode, or1, or2),
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const_true_rtx));
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or_result = gen_reg_rtx (CCFPmode);
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cmp = gen_e500_cr_ior_compare (or_result, compare_result,
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compare_result2);
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compare_result = or_result;
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code = EQ;
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}
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@ -10229,9 +10221,9 @@ rs6000_emit_sCOND (enum rtx_code code, rtx result)
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abort ();
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if (cond_code == NE)
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emit_insn (gen_e500_flip_eq_bit (t, t));
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emit_insn (gen_e500_flip_gt_bit (t, t));
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emit_insn (gen_move_from_CR_eq_bit (result, t));
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emit_insn (gen_move_from_CR_gt_bit (result, t));
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return;
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}
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@ -10412,9 +10404,9 @@ output_cbranch (rtx op, const char *label, int reversed, rtx insn)
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return string;
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}
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/* Return the string to flip the EQ bit on a CR. */
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/* Return the string to flip the GT bit on a CR. */
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char *
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output_e500_flip_eq_bit (rtx dst, rtx src)
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output_e500_flip_gt_bit (rtx dst, rtx src)
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{
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static char string[64];
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int a, b;
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@ -10423,9 +10415,9 @@ output_e500_flip_eq_bit (rtx dst, rtx src)
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|| GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
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abort ();
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/* EQ bit. */
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a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
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b = 4 * (REGNO (src) - CR0_REGNO) + 2;
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/* GT bit. */
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a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
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b = 4 * (REGNO (src) - CR0_REGNO) + 1;
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sprintf (string, "crnot %d,%d", a, b);
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return string;
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@ -50,7 +50,7 @@
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(UNSPEC_TLSGOTTPREL 28)
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(UNSPEC_TLSTLS 29)
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(UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
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(UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit
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(UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
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])
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;;
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@ -11476,11 +11476,11 @@
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(set_attr "length" "8")])
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;; Same as above, but get the GT bit.
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(define_insn "move_from_CR_eq_bit"
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(define_insn "move_from_CR_gt_bit"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))]
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(unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
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"TARGET_E500"
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1"
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"mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
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[(set_attr "type" "mfcr")
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(set_attr "length" "8")])
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@ -29,6 +29,7 @@
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(TSTDFGT_GPR 1009)
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(CMPDFLT_GPR 1010)
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(TSTDFLT_GPR 1011)
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(E500_CR_IOR_COMPARE 1012)
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])
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(define_insn "*negsf2_gpr"
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@ -2615,14 +2616,14 @@
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;; FP comparison stuff.
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;; Flip the GT bit.
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(define_insn "e500_flip_eq_bit"
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(define_insn "e500_flip_gt_bit"
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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(unspec:CCFP
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[(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
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"!TARGET_FPRS && TARGET_HARD_FLOAT"
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"*
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{
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return output_e500_flip_eq_bit (operands[0], operands[1]);
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return output_e500_flip_gt_bit (operands[0], operands[1]);
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}"
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[(set_attr "type" "cr_logical")])
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@ -2751,3 +2752,13 @@
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"TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
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"efdtstlt %0,%1,%2"
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[(set_attr "type" "veccmpsimple")])
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;; Like cceq_ior_compare, but compare the GT bits.
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(define_insn "e500_cr_ior_compare"
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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(unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
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(match_operand 2 "cc_reg_operand" "y")]
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E500_CR_IOR_COMPARE))]
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"TARGET_E500"
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"cror 4*%0+gt,4*%1+gt,4*%2+gt"
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[(set_attr "type" "cr_logical")])
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