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oops - omiited from previous delta:
* Contributed support for the Cirrus EP9312 "Maverick"
floating point co-processor. Written by Aldy Hernandez
<aldyh@redhat.com>.
(config/arm/arm.c): Add Cirrus support.
(config/arm/arm.h): Likewise.
(config/arm/aout.h): Likewise.
(config/arm/arm.md): Likewise.
(config/arm/arm-protos.h): Likewise.
(config.gcc): Likewise.
(doc/invoke.texi): Describe new -mcpu value and new
-mcirrus-fix-invalid-insns switch,
(cirrus.md): New file.
From-SVN: r62626
This commit is contained in:
Nick Clifton
parent
9b6b54e2fe
commit
63a3b0a700
667
gcc/config/arm/cirrus.md
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667
gcc/config/arm/cirrus.md
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;; Cirrus EP9312 "Maverick" ARM floating point co-processor description.
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;; Copyright (C) 2003 Free Software Foundation, Inc.
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;; Contributed by Red Hat.
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;; Written by Aldy Hernandez (aldyh@redhat.com)
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;; This file is part of GNU CC.
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GNU CC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA.
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(define_attr "cirrus_fpu" "fpa,fpe2,fpe3,yes" (const (symbol_ref "arm_fpu_attr")))
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; Classification of each insn
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; farith Floating point arithmetic (4 cycle)
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; dmult Double multiplies (7 cycle)
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(define_attr "cirrus_type" "normal,farith,dmult" (const_string "normal"))
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; Cirrus types for invalid insn combinations
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; no Not a cirrus insn
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; yes Cirrus insn
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; double cfldrd, cfldr64, cfstrd, cfstr64
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; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
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; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
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(define_attr "cirrus" "no,yes,double,compare,move" (const_string "no"))
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(define_function_unit "cirrus_fpa" 1 0
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(and (eq_attr "cirrus_fpu" "yes")
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(eq_attr "cirrus_type" "farith")) 4 1)
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(define_function_unit "cirrus_fpa" 1 0
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(and (eq_attr "cirrus_fpu" "yes")
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(eq_attr "cirrus_type" "dmult")) 7 4)
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(define_function_unit "cirrus_fpa" 1 0
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(and (eq_attr "cirrus_fpu" "yes")
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(eq_attr "cirrus_type" "normal")) 1 1)
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(define_insn "cirrus_adddi3"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:DI 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfadd64%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "*cirrus_addsi3"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfadd32%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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;; define_insn replaced by define_expand and define_insn
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(define_expand "addsf3"
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[(set (match_operand:SF 0 "s_register_operand" "")
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(plus:SF (match_operand:SF 1 "s_register_operand" "")
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(match_operand:SF 2 "fpu_add_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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"
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if (TARGET_CIRRUS
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&& !cirrus_fp_register (operands[2], SFmode))
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operands[2] = force_reg (SFmode, operands[2]);
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")
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(define_insn "*cirrus_addsf3"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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(match_operand:SF 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfadds%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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;; define_insn replaced by define_expand and define_insn
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(define_expand "adddf3"
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[(set (match_operand:DF 0 "s_register_operand" "")
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(plus:DF (match_operand:DF 1 "s_register_operand" "")
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(match_operand:DF 2 "fpu_add_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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"
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if (TARGET_CIRRUS
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&& !cirrus_fp_register (operands[2], DFmode))
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operands[2] = force_reg (DFmode, operands[2]);
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")
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(define_insn "*cirrus_adddf3"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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(match_operand:DF 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfaddd%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "cirrus_subdi3"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:DI 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfsub64%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "*cirrus_subsi3_insn"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfsub32%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_expand "subsf3"
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[(set (match_operand:SF 0 "s_register_operand" "")
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(minus:SF (match_operand:SF 1 "fpu_rhs_operand" "")
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(match_operand:SF 2 "fpu_rhs_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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"
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if (TARGET_CIRRUS)
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{
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if (!cirrus_fp_register (operands[1], SFmode))
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operands[1] = force_reg (SFmode, operands[1]);
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if (!cirrus_fp_register (operands[2], SFmode))
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operands[2] = force_reg (SFmode, operands[2]);
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}
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")
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(define_insn "*cirrus_subsf3"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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(match_operand:SF 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfsubs%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_expand "subdf3"
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[(set (match_operand:DF 0 "s_register_operand" "")
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(minus:DF (match_operand:DF 1 "fpu_rhs_operand" "")
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(match_operand:DF 2 "fpu_rhs_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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"
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if (TARGET_CIRRUS)
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{
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if (!cirrus_fp_register (operands[1], DFmode))
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operands[1] = force_reg (DFmode, operands[1]);
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if (!cirrus_fp_register (operands[2], DFmode))
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operands[2] = force_reg (DFmode, operands[2]);
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}
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")
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(define_insn "*cirrus_subdf3"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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(match_operand:DF 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfsubd%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "*cirrus_mulsi3"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
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(match_operand:SI 1 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfmul32%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "muldi3"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
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(match_operand:DI 1 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfmul64%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "dmult")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "*cirrus_mulsi3addsi"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(plus:SI
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(mult:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_fp_register" "v"))
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(match_operand:SI 3 "cirrus_fp_register" "0")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfmac32%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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;; Cirrus SI multiply-subtract
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(define_insn "*cirrus_mulsi3subsi"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(minus:SI
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(match_operand:SI 1 "cirrus_fp_register" "0")
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(mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
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(match_operand:SI 3 "cirrus_fp_register" "v"))))]
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"0 && TARGET_ARM && TARGET_CIRRUS"
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"cfmsc32%?\\t%V0, %V2, %V3"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_expand "mulsf3"
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[(set (match_operand:SF 0 "s_register_operand" "")
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(mult:SF (match_operand:SF 1 "s_register_operand" "")
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(match_operand:SF 2 "fpu_rhs_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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"
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if (TARGET_CIRRUS
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&& !cirrus_fp_register (operands[2], SFmode))
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operands[2] = force_reg (SFmode, operands[2]);
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")
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(define_insn "*cirrus_mulsf3"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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(match_operand:SF 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfmuls%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "farith")
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(set_attr "cirrus" "yes")]
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)
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(define_expand "muldf3"
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[(set (match_operand:DF 0 "s_register_operand" "")
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(mult:DF (match_operand:DF 1 "s_register_operand" "")
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(match_operand:DF 2 "fpu_rhs_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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"
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if (TARGET_CIRRUS
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&& !cirrus_fp_register (operands[2], DFmode))
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operands[2] = force_reg (DFmode, operands[2]);
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")
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(define_insn "*cirrus_muldf3"
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[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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(mult:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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(match_operand:DF 2 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfmuld%?\\t%V0, %V1, %V2"
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[(set_attr "cirrus_type" "dmult")
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(set_attr "cirrus" "yes")]
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)
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(define_insn "cirrus_ashl_const"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfsh32%?\\t%V0, %V1, #%s2"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "cirrus_ashiftrt_const"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfsh32%?\\t%V0, %V1, #-%s2"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "cirrus_ashlsi3"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfrshl32%?\\t%V1, %V0, %s2"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "ashldi3_cirrus"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "register_operand" "r")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfrshl64%?\\t%V1, %V0, %s2"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "cirrus_ashldi_const"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfsh64%?\\t%V0, %V1, #%s2"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "cirrus_ashiftrtdi_const"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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(match_operand:SI 2 "cirrus_shift_const" "")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfsh64%?\\t%V0, %V1, #-%s2"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "*cirrus_absdi2"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfabs64%?\\t%V0, %V1"
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[(set_attr "cirrus" "yes")]
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)
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;; This doesn't really clobber ``cc''. Fixme: aldyh.
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(define_insn "*cirrus_negdi2"
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[(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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(neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARM && TARGET_CIRRUS"
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"cfneg64%?\\t%V0, %V1"
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[(set_attr "cirrus" "yes")]
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)
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(define_insn "*cirrus_negsi2"
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[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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(neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
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"TARGET_ARM && TARGET_CIRRUS && 0"
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"cfneg32%?\\t%V0, %V1"
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[(set_attr "cirrus" "yes")]
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)
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(define_expand "negsf2"
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[(set (match_operand:SF 0 "s_register_operand" "")
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(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
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"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
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""
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)
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(define_insn "*cirrus_negsf2"
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[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfnegs%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_expand "negdf2"
|
||||
[(set (match_operand:DF 0 "s_register_operand" "")
|
||||
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"")
|
||||
|
||||
(define_insn "*cirrus_negdf2"
|
||||
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
|
||||
(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfnegd%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_expand "abssi2"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "s_register_operand" "")
|
||||
(abs:SI (match_operand:SI 1 "s_register_operand" "")))
|
||||
(clobber (reg:CC CC_REGNUM))])]
|
||||
"TARGET_ARM"
|
||||
"")
|
||||
|
||||
;; This doesn't really clobber the condition codes either.
|
||||
(define_insn "*cirrus_abssi2"
|
||||
[(set (match_operand:SI 0 "cirrus_fp_register" "=v")
|
||||
(abs:SI (match_operand:SI 1 "cirrus_fp_register" "v")))
|
||||
(clobber (reg:CC CC_REGNUM))]
|
||||
"TARGET_ARM && TARGET_CIRRUS && 0"
|
||||
"cfabs32%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_expand "abssf2"
|
||||
[(set (match_operand:SF 0 "s_register_operand" "")
|
||||
(abs:SF (match_operand:SF 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"")
|
||||
|
||||
(define_insn "*cirrus_abssf2"
|
||||
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
|
||||
(abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfabss%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_expand "absdf2"
|
||||
[(set (match_operand:DF 0 "s_register_operand" "")
|
||||
(abs:DF (match_operand:DF 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"")
|
||||
|
||||
(define_insn "*cirrus_absdf2"
|
||||
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
|
||||
(abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfabsd%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_expand "floatsisf2"
|
||||
[(set (match_operand:SF 0 "s_register_operand" "")
|
||||
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"
|
||||
if (TARGET_CIRRUS)
|
||||
{
|
||||
emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
")
|
||||
|
||||
;; Convert Cirrus-SI to Cirrus-SF
|
||||
(define_insn "cirrus_floatsisf2"
|
||||
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
|
||||
(float:SF (match_operand:SI 1 "s_register_operand" "r")))
|
||||
(clobber (match_scratch:DF 2 "=v"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cirrus" "move")]
|
||||
)
|
||||
|
||||
(define_expand "floatsidf2"
|
||||
[(set (match_operand:DF 0 "s_register_operand" "")
|
||||
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"
|
||||
if (TARGET_CIRRUS)
|
||||
{
|
||||
emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
")
|
||||
|
||||
(define_insn "cirrus_floatsidf2"
|
||||
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
|
||||
(float:DF (match_operand:SI 1 "s_register_operand" "r")))
|
||||
(clobber (match_scratch:DF 2 "=v"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cirrus" "move")]
|
||||
)
|
||||
|
||||
(define_insn "floatdisf2"
|
||||
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
|
||||
(float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfcvt64s%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")])
|
||||
|
||||
(define_insn "floatdidf2"
|
||||
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
|
||||
(float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfcvt64d%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")])
|
||||
|
||||
(define_expand "fix_truncsfsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "")
|
||||
(fix:SI (match_operand:SF 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"
|
||||
if (TARGET_CIRRUS)
|
||||
{
|
||||
if (!cirrus_fp_register (operands[0], SImode))
|
||||
operands[0] = force_reg (SImode, operands[0]);
|
||||
if (!cirrus_fp_register (operands[1], SFmode))
|
||||
operands[1] = force_reg (SFmode, operands[0]);
|
||||
emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
")
|
||||
|
||||
(define_insn "cirrus_truncsfsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(fix:SI (match_operand:SF 1 "cirrus_fp_register" "v")))
|
||||
(clobber (match_scratch:DF 2 "=v"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
|
||||
[(set_attr "length" "8")
|
||||
(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_expand "fix_truncdfsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "")
|
||||
(fix:SI (match_operand:DF 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
"
|
||||
if (TARGET_CIRRUS)
|
||||
{
|
||||
if (!cirrus_fp_register (operands[1], DFmode))
|
||||
operands[1] = force_reg (DFmode, operands[0]);
|
||||
emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1]));
|
||||
DONE;
|
||||
}
|
||||
")
|
||||
|
||||
(define_insn "cirrus_truncdfsi2"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(fix:SI (match_operand:DF 1 "cirrus_fp_register" "v")))
|
||||
(clobber (match_scratch:DF 2 "=v"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
|
||||
[(set_attr "length" "8")]
|
||||
)
|
||||
|
||||
(define_expand "truncdfsf2"
|
||||
[(set (match_operand:SF 0 "s_register_operand" "")
|
||||
(float_truncate:SF
|
||||
(match_operand:DF 1 "s_register_operand" "")))]
|
||||
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
|
||||
""
|
||||
)
|
||||
|
||||
(define_insn "*cirrus_truncdfsf2"
|
||||
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
|
||||
(float_truncate:SF
|
||||
(match_operand:DF 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfcvtds%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*cirrus_extendsfdf2"
|
||||
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
|
||||
(float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"cfcvtsd%?\\t%V0, %V1"
|
||||
[(set_attr "cirrus" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*cirrus_arm_movdi"
|
||||
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
|
||||
(match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,m,v,v"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS"
|
||||
"*
|
||||
{
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
return (output_move_double (operands));
|
||||
|
||||
case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
|
||||
case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
|
||||
|
||||
case 5: return \"cfldr64%?\\t%V0, %1\";
|
||||
case 6: return \"cfstr64%?\\t%V1, %0\";
|
||||
|
||||
/* Shifting by 0 will just copy %1 into %0. */
|
||||
case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
|
||||
|
||||
default: abort ();
|
||||
}
|
||||
}"
|
||||
[(set_attr "length" "8,8,8,8,8,4,4,4")
|
||||
(set_attr "type" "*,load,store2,*,*,load,store2,*")
|
||||
(set_attr "pool_range" "*,1020,*,*,*,*,*,*")
|
||||
(set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")
|
||||
(set_attr "cirrus" "no,no,no,move,yes,double,double,yes")]
|
||||
)
|
||||
|
||||
;; Cirrus SI values have been outlawed. Look in arm.h for the comment
|
||||
;; on HARD_REGNO_MODE_OK.
|
||||
|
||||
(define_insn "*cirrus_arm_movsi_insn"
|
||||
[(set (match_operand:SI 0 "general_operand" "=r,r,r,m,*v,r,*v,T,*v")
|
||||
(match_operand:SI 1 "general_operand" "rI,K,mi,r,r,*v,T,*v,*v"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS && 0
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| register_operand (operands[1], SImode))"
|
||||
"@
|
||||
mov%?\\t%0, %1
|
||||
mvn%?\\t%0, #%B1
|
||||
ldr%?\\t%0, %1
|
||||
str%?\\t%1, %0
|
||||
cfmv64lr%?\\t%Z0, %1
|
||||
cfmvr64l%?\\t%0, %Z1
|
||||
cfldr32%?\\t%V0, %1
|
||||
cfstr32%?\\t%V1, %0
|
||||
cfsh32%?\\t%V0, %V1, #0"
|
||||
[(set_attr "type" "*,*,load,store1,*,*,load,store1,*")
|
||||
(set_attr "pool_range" "*,*,4096,*,*,*,1024,*,*")
|
||||
(set_attr "neg_pool_range" "*,*,4084,*,*,*,1012,*,*")
|
||||
(set_attr "cirrus" "no,no,no,no,move,yes,yes,yes,yes")]
|
||||
)
|
||||
|
||||
(define_insn "*cirrus_movsf_hard_insn"
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
|
||||
(match_operand:SF 1 "general_operand" "v,m,r,v,v,r,mE,r"))]
|
||||
"TARGET_ARM && TARGET_CIRRUS
|
||||
&& (GET_CODE (operands[0]) != MEM
|
||||
|| register_operand (operands[1], SFmode))"
|
||||
"@
|
||||
cfcpys%?\\t%V0, %V1
|
||||
cfldrs%?\\t%V0, %1
|
||||
cfmvsr%?\\t%V0, %1
|
||||
cfmvrs%?\\t%0, %V1
|
||||
cfstrs%?\\t%V1, %0
|
||||
mov%?\\t%0, %1
|
||||
ldr%?\\t%0, %1\\t%@ float
|
||||
str%?\\t%1, %0\\t%@ float"
|
||||
[(set_attr "length" "*,*,*,*,*,4,4,4")
|
||||
(set_attr "type" "*,load,*,*,store1,*,load,store1")
|
||||
(set_attr "pool_range" "*,*,*,*,*,*,4096,*")
|
||||
(set_attr "neg_pool_range" "*,*,*,*,*,*,4084,*")
|
||||
(set_attr "cirrus" "yes,yes,move,yes,yes,no,no,no")]
|
||||
)
|
||||
|
||||
(define_insn "*cirrus_movdf_hard_insn"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
|
||||
(match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,m,r,v,v"))]
|
||||
"TARGET_ARM
|
||||
&& TARGET_CIRRUS
|
||||
&& (GET_CODE (operands[0]) != MEM
|
||||
|| register_operand (operands[1], DFmode))"
|
||||
"*
|
||||
{
|
||||
switch (which_alternative)
|
||||
{
|
||||
case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
|
||||
case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
|
||||
case 2: case 3: case 4: return output_move_double (operands);
|
||||
case 5: return \"cfcpyd%?\\t%V0, %V1\";
|
||||
case 6: return \"cfldrd%?\\t%V0, %1\";
|
||||
case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
|
||||
case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
|
||||
case 9: return \"cfstrd%?\\t%V1, %0\";
|
||||
default: abort ();
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "load,store2,*,store2,load,*,load,*,*,store2")
|
||||
(set_attr "length" "4,4,8,8,8,4,4,8,8,4")
|
||||
(set_attr "pool_range" "*,*,*,*,252,*,*,*,*,*")
|
||||
(set_attr "neg_pool_range" "*,*,*,*,244,*,*,*,*,*")
|
||||
(set_attr "cirrus" "no,no,no,no,no,yes,double,move,yes,double")]
|
||||
)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user