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RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

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Use Zbs when generating a sequence for
   "if ((a & twobits) == singlebit) ..."
that can be expressed as
   bexti + bexti + andn.

gcc/ChangeLog:

	* config/riscv/bitmanip.md
	(*branch<X:mode>_mask_twobits_equals_singlebit):
	Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C
	has one	of these tow bits set.
	* config/riscv/predicates.md (const_twobits_not_arith_operand):
	New predicate.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbs-if_then_else-01.c: New test.
This commit is contained in:
Philipp Tomsich 2022-10-16 12:48:26 +02:00
parent bc6beecb4d
commit 60d2bcc55b
3 changed files with 67 additions and 0 deletions
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42
gcc/config/riscv/bitmanip.md
View File

@ -595,3 +595,45 @@
operands[3] = GEN_INT (bits | topbit);
operands[4] = GEN_INT (~topbit);
})
;; IF_THEN_ELSE: test for 2 bits of opposite polarity
(define_insn_and_split "*branch<X:mode>_mask_twobits_equals_singlebit"
[(set (pc)
(if_then_else
(match_operator 1 "equality_operator"
[(and:X (match_operand:X 2 "register_operand" "r")
(match_operand:X 3 "const_twobits_not_arith_operand" "i"))
(match_operand:X 4 "single_bit_mask_operand" "i")])
(label_ref (match_operand 0 "" ""))
(pc)))
(clobber (match_scratch:X 5 "=&r"))
(clobber (match_scratch:X 6 "=&r"))]
"TARGET_ZBS && TARGET_ZBB"
"#"
"&& reload_completed"
[(set (match_dup 5) (zero_extract:X (match_dup 2)
(const_int 1)
(match_dup 8)))
(set (match_dup 6) (zero_extract:X (match_dup 2)
(const_int 1)
(match_dup 9)))
(set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5)))
(set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)])
(label_ref (match_dup 0))
(pc)))]
{
unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]);
unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]);
/* We should never see an unsatisfiable condition. */
gcc_assert (twobits_mask & singlebit_mask);
int setbit = ctz_hwi (singlebit_mask);
int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask);
operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE,
<X:MODE>mode, operands[6], GEN_INT(0));
operands[8] = GEN_INT (setbit);
operands[9] = GEN_INT (clearbit);
})

5
gcc/config/riscv/predicates.md
View File

@ -310,6 +310,11 @@
(and (match_code "const_int")
(match_test "popcount_hwi (UINTVAL (op)) == 2")))
(define_predicate "const_twobits_not_arith_operand"
(and (match_code "const_int")
(and (not (match_operand 0 "arith_operand"))
(match_operand 0 "const_twobits_operand"))))
;; A CONST_INT operand that fits into the unsigned half of a
;; signed-immediate after the top bit has been cleared
(define_predicate "uimm_extra_bit_operand"

20
gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c Normal file
View File

@ -0,0 +1,20 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */
/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
void g();
void f1 (long a)
{
if ((a & ((1ul << 33) | (1 << 4))) == (1ul << 33))
g();
}
void f2 (long a)
{
if ((a & 0x12) == 0x10)
g();
}
/* { dg-final { scan-assembler-times "bexti\t" 2 } } */
/* { dg-final { scan-assembler-times "andn\t" 1 } } */